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HT46R068B 参数 Datasheet PDF下载

HT46R068B图片预览
型号: HT46R068B
PDF下载: 下载PDF文件 查看货源
内容描述: 增强A / D型8位OTP MCU [Enhanced A/D Type 8-bit OTP MCU]
分类和应用:
文件页数/大小: 134 页 / 5896 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT46R068B/HT46R069B  
Enhanced A/D Type 8-bit OTP MCU  
Interrupts  
Interrupts are an important part of any microcontroller system. When an external event or an  
internal function such as a Timer/Event Counter or Time Base requires microcontroller attention,  
their corresponding interrupt will enforce a temporary suspension of the main program allowing  
the microcontroller to direct attention to their respective needs.  
The device contains a single external interrupt and multiple internal interrupts. The external  
interrupt is controlled by the action of the external interrupt pin, while the internal interrupts are  
generated by the various functions such as Timer/Event Counters, and Time Base.  
Interrupt Register  
Overall interrupt control, which means interrupt enabling and request flag setting, is controlled  
by using two registers, INTC0 and INTC1. By controlling the appropriate enable bits in this  
registers each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the  
corresponding request flag will be set by the microcontroller. The global enable flag if cleared to  
zero will disable all interrupts.  
INTC0 Register  
Bit  
Name  
R/W  
7
6
5
4
EIF  
R/W  
0
3
2
1
EEI  
R/W  
0
0
T1F  
R/W  
0
T0F  
R/W  
0
ET1I  
R/W  
0
ET0I  
R/W  
0
EMI  
R/W  
0
POR  
Bit 7  
unimplemented, read as “0”  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
T1F: Timer/Event Counter 1 interrupt request flag  
0: inactive  
1: active  
T0F: Timer/Event Counter 0 interrupt request flag  
0: inactive  
1: active  
EIF: External interrupt request flag  
0: inactive  
1: active  
ET1I: Timer/Event Counter 1 interrupt enable  
0: disable  
1: enable  
ET0I: Timer/Event Counter 0 interrupt enable  
0: disable  
1: enable  
EEI: External interrupt enable  
0: disable  
1: enable  
EMI: Master interrupt global enable  
0: disable  
1: enable  
Rev. 1.00  
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