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HT46R068B 参数 Datasheet PDF下载

HT46R068B图片预览
型号: HT46R068B
PDF下载: 下载PDF文件 查看货源
内容描述: 增强A / D型8位OTP MCU [Enhanced A/D Type 8-bit OTP MCU]
分类和应用:
文件页数/大小: 134 页 / 5896 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
 浏览型号HT46R068B的Datasheet PDF文件第40页浏览型号HT46R068B的Datasheet PDF文件第41页浏览型号HT46R068B的Datasheet PDF文件第42页浏览型号HT46R068B的Datasheet PDF文件第43页浏览型号HT46R068B的Datasheet PDF文件第45页浏览型号HT46R068B的Datasheet PDF文件第46页浏览型号HT46R068B的Datasheet PDF文件第47页浏览型号HT46R068B的Datasheet PDF文件第48页  
HT46R068B/HT46R069B  
Enhanced A/D Type 8-bit OTP MCU  
Reset Initial Conditions  
The different types of reset described affect the reset flags in different ways. These flags, known  
as PDF and TO are located in the status register and are controlled by various microcontroller  
operations, such as the Idle/Sleep function or Watchdog Timer. The reset flags are shown in the  
table:  
TO  
0
1
1
PDF  
RESET Conditions  
0
1
Poweꢁ-on ꢁeset  
RES oꢁ LVR ꢁeset dꢀꢁing Noꢁmal oꢁ Slow Mode opeꢁation  
WDT time-oꢀt ꢁeset dꢀꢁing Noꢁmal oꢁ Slow Mode opeꢁation  
WDT time-oꢀt ꢁeset dꢀꢁing Idle oꢁ Sleep Mode opeꢁation  
Note: "u" stands for unchanged  
The following table indicates the way in which the various components of the microcontroller are  
affected after a power-on reset occurs.  
Item  
Pꢁogꢁam Coꢀnteꢁ  
Inteꢁꢁꢀpts  
Condition After RESET  
Reset to zeꢁo  
All inteꢁꢁꢀpts will be disabled  
WDT  
Cleaꢁ afteꢁ ꢁesetꢅ WDT begins coꢀnting  
Timeꢁ Coꢀnteꢁ will be tꢀꢁned off  
The Timeꢁ Coꢀnteꢁ Pꢁescaleꢁ will be cleaꢁed  
I/O poꢁts will be setꢀp as inpꢀts  
Timeꢁ/Event Coꢀnteꢁ  
Pꢁescaleꢁ  
Inpꢀt/Oꢀtpꢀt Poꢁts  
Stack Pointeꢁ  
Stack Pointeꢁ will point to the top of the stack  
The different kinds of resets all affect the internal registers of the microcontroller in different ways.  
To ensure reliable continuation of normal program execution after a reset occurs, it is important to  
know what condition the microcontroller is in after a particular reset occurs. The following table  
describes how each type of reset affects each of the microcontroller internal registers.  
RES or LVR  
Reset  
(Normal  
RES or LVR  
Reset  
(Idle/Sleep)  
WDT Time-out  
(Normal  
Operation)  
Power-on  
Reset  
WDT Time-out  
(Idle/Sleep)  
Register  
Operation)  
PCL  
MP0  
0 0 0 0 0 0 0 0  
x x x x x x x x  
x x x x x x x x  
– – 0 – – – 0 0  
– 0 0 – – 0 0 0  
x x x x x x x x  
x x x x x x x x  
x x x x x x x x  
– – – – – 1 1 1  
– – 0 0 x x x x  
– 0 0 0 0 0 0 0  
– 0 – 0 – 0 – 0  
– 0 0 0 – 0 0 0  
– 0 0 0 – 0 0 0  
x x x x x x x x  
0 0 0 0 1 0 0 0  
x x x x x x x x  
0 0 0 0 1 – – –  
x x x x x x x x  
0 0 0 0 0 0 0 0  
x x x x x x x x  
x x x x x x x x  
– – 0 – – – 0 0  
– 0 0 – – 0 0 0  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
– – – – – 1 1 1  
– – ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
– 0 0 0 0 0 0 0  
– 0 – 0 – 0 – 0  
– 0 0 0 – 0 0 0  
– 0 0 0 – 0 0 0  
x x x x x x x x  
0 0 0 0 1 0 0 0  
x x x x x x x x  
0 0 0 0 1 – – –  
x x x x x x x x  
0 0 0 0 0 0 0 0  
x x x x x x x x  
x x x x x x x x  
– – 0 – – – 0 0  
– 0 0 – – 0 0 0  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
– – – – – 1 1 1  
– – 0 1 ꢀ ꢀ ꢀ ꢀ  
– 0 0 0 0 0 0 0  
– 0 – 0 – 0 – 0  
– 0 0 0 – 0 0 0  
– 0 0 0 – 0 0 0  
x x x x x x x x  
0 0 0 0 1 0 0 0  
x x x x x x x x  
0 0 0 0 1 – – –  
x x x x x x x x  
0 0 0 0 0 0 0 0  
x x x x x x x x  
x x x x x x x x  
– – 0 – – – 0 0  
– 0 0 – – 0 0 0  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
– – – – – 1 1 1  
– – 1 ꢀ ꢀ ꢀ ꢀ ꢀ  
– 0 0 0 0 0 0 0  
– 0 – 0 – 0 – 0  
– 0 0 0 – 0 0 0  
– 0 0 0 – 0 0 0  
x x x x x x x x  
0 0 0 0 1 0 0 0  
x x x x x x x x  
0 0 0 0 1 – – –  
x x x x x x x x  
0 0 0 0 0 0 0 0  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
– – ꢀ – – – ꢀ ꢀ  
– ꢀ ꢀ – – ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
– – – – – ꢀ ꢀ ꢀ  
– – 1 1 ꢀ ꢀ ꢀ ꢀ  
– ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
– ꢀ – ꢀ – ꢀ – ꢀ  
– ꢀ ꢀ ꢀ – ꢀ ꢀ ꢀ  
– ꢀ ꢀ ꢀ – ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
ꢀ ꢀ ꢀ ꢀ ꢀ – – –  
ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ ꢀ  
MP1  
BP  
BP  
ACC  
TBLP  
TBLH  
WDTS  
STATUS  
INTC0  
INTC1  
MFIC  
TMR0  
TMR0C  
TMR1  
TMR1C  
TMRꢃL  
Rev. 1.00  
39  
�anꢀaꢁꢂ ꢃꢄꢅ ꢃ011  
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