HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
● HT46R069B
Bit
Register
Name
POR
7
6
5
4
3
2
1
0
PAWK
PAC
00H
FFH
00H
FFH
00H
FFH
00H
FFH
00H
FFH
00H
FFH
00H
FFH
00H
3FH
00H
PAWK7 PAWKꢄ PAWK5 PAWK4 PAWK3 PAWKꢃ PAWK1 PAWK0
PAC7
—
PACꢄ
PAPUꢄ PAPU5 PAPU4 PAPU3 PAPUꢃ PAPU1 PAPU0
PBCꢄ PBC5 PBC4 PBC3 PBCꢃ PBC1 PBC0
PAC5
PAC4
PAC3
PACꢃ
PAC1
PAC0
PAPU
PBC
PBC7
PBPU
PCC
PBPU7 PBPUꢄ PBPU5 PBPU4 PBPU3 PBPUꢃ PBPU1 PBPU0
PCC7 PCCꢄ PCC5 PCC4 PCC3 PCCꢃ PCC1 PCC0
PCPU7 PCPUꢄ PCPU5 PCPU4 PCPU3 PCPUꢃ PCPU1 PCPU0
PDC7 PDCꢄ PDC5 PDC4 PDC3 PDCꢃ PDC1 PDC0
PDPU7 PDPUꢄ PDPU5 PDPU4 PDPU3 PDPUꢃ PDPU1 PDPU0
PEC7 PECꢄ PEC5 PEC4 PEC3 PECꢃ PEC1 PEC0
PEPU7 PEPUꢄ PEPU5 PEPU4 PEPU3 PEPUꢃ PEPU1 PEPU0
PFC7 PFCꢄ PFC5 PFC4 PFC3 PFCꢃ PFC1 PFC0
PFPU7 PFPUꢄ PFPU5 PFPU4 PFPU3 PFPUꢃ PFPU1 PFPU0
PGC7 PGCꢄ PGC5 PGC4 PGC3 PGCꢃ PGC1 PGC0
PGPU7 PGPUꢄ PGPU5 PGPU4 PGPU3 PGPUꢃ PGPU1 PGPU0
PCPU
PDC
PDPU
PEC
PEPU
PFC
PFPU
PGC
PGPU
PHC
—
—
—
—
PHC5
PHC4
PHC3
PHCꢃ
PHC1
PHC0
PHPU
PHPU5 PHPU4 PHPU3 PHPUꢃ PHPU1 PHPU0
"—" Unimplemented, read as "0"
PAWKn: PA wake-up function enable
0: disable
1: enable
PACn/PBCn/PCCn/PDCn/PECn/PFCn/PGCn/PHCn: I/O type selection
0: output
1: input
PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn/PGPUn/PHPUn: Pull-high function enable
0: disable
1: enable
I/O Port Control Registers
Each Port has its own control register, known as PAC, PBC, PCC, PDC, PEC, PFC, PGC, PHC
which controls the input/output configuration. With this control register, each I/O pin with or
without pull-high resistors can be reconfigured dynamically under software control. For the I/O
pin to function as an input, the corresponding bit of the control register must be written as a "1".
This will then allow the logic state of the input pin to be directly read by instructions. When the
corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS
output. If the pin is currently setup as an output, instructions can still be used to read the output
register. However, it should be noted that the program will in fact only read the status of the output
data latch and not the actual logic status of the output pin.
Rev. 1.00
43
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