HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
Watchdog Timer
The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused
by the program jumping to unknown locations due to certain uncontrollable external events such as
electrical noise.
Watchdog Timer Operation
It operates by providing a device reset when the Watchdog Timer counter overflows. Note that if
the Watchdog Timer function is not enabled, then any instructions related to the Watchdog Timer
will result in no operation.
Setting up the various Watchdog Timer options are controlled via the configuration options and
two internal registers WDTS and CTRL1. Enabling the Watchdog Timer can be controlled by both
a configuration option and the WDTEN bits in the CTRL1 internal register in the Data Memory.
Configuration Option
Disable
CTRL1 Register
WDT Function
Disable
Enable
x
OFF
ON
ON
Disable
Enable
Watchdog Timer On/Off Control
The Watchdog Timer will be disabled if bits WDTEN3~WDTEN0 in the CTRL1 register are
written with the binary value 1010B and WDT configuration option is disable. This will be the
condition when the device is powered up. Although any other data written to WDTEN3~WDTEN0
will ensure that the Watchdog Timer is enabled, for maximum protection it is recommended that
the value 0101B is written to these bits.
The Watchdog Timer clock can emanate from three different sources, selected by configuration
option. These are LXT, fSYS/4, or LIRC. It is important to note that when the system enters the Idle/
Sleep Mode the instruction clock is stopped, therefore if the configuration options have selected
fSYS/4 as the Watchdog Timer clock source, the Watchdog Timer will cease to function. For systems
that operate in noisy environments, using the LIRC or the LXT as the clock source is therefore
the recommended choice. The division ratio of the prescaler is determined by bits 0, 1 and 2 of
the WDTS register, known as WS0, WS1 and WS2. If the Watchdog Timer internal clock source
is selected and with the WS0, WS1 and WS2 bits of the WDTS register all set high, the prescaler
division ratio will be 1:128, which will give a maximum time-out period.
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and
set the status bit TO. However, if the system is in the Idle/Sleep Mode, when a Watchdog Timer
time-out occurs, the device will be woken up, the TO bit in the status register will be set and only
the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the
contents of the Watchdog Timer. The first is an external hardware reset, which means a low level on
the external reset pin, the second is using the Clear Watchdog Timer software instructions and the
third is when a HALT instruction is executed. There are two methods of using software instructions
to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option
is to use the single "CLR WDT" instruction while the second is to use the two commands "CLR
WDT1" and "CLR WDT2". For the first option, a simple execution of "CLR WDT" will clear the
Watchdog Timer while for the second option, both "CLR WDT1" and "CLR WDT2" must both
be executed to successfully clear the Watchdog Timer. Note that for this second option, if "CLR
WDT1" is used to clear the Watchdog Timer, successive executions of this instruction will have no
effect, only the execution of a "CLR WDT2" instruction will clear the Watchdog Timer. Similarly
after the "CLR WDT2" instruction has been executed, only a successive "CLR WDT1" instruction
can clear the Watchdog Timer.
Rev. 1.00
35
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HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
