HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
RES Pin Reset
●
This type of reset occurs when the microcontroller is already running and the RES pin is forcefully
pulled low by external hardware such as an external switch. In this case as in the case of other
reset, the Program Counter will reset to zero and program execution initiated from this point.
0
9
.
V
D
D
0
4
.
V
D
D
R
S
E
t
R
T
S
D
+
t
S
S
T
t
n
r
e
n
a
R
e
l
e
s
t
RES Reset Timing Chart
Note: tRSTD is power-on delay, typical time=100ms
Low Voltage Reset — LVR
●
The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of
the device. The LVR function is selected via a configuration option. If the supply voltage of the
device drops to within a range of 0.9V~VLVR such as might occur when changing the battery, the
LVR will automatically reset the device internally. For a valid LVR signal, a low supply voltage,
i.e., a voltage in the range between 0.9V~VLVR must exist for a time greater than that specified
by tLVR in the A.C. characteristics. If the low supply voltage state does not exceed this value, the
LVR will ignore the low supply voltage and will not perform a reset function. The actual VLVR
value can be selected via configuration options.
L
R
V
t
R
T
S
D
+
t
S
S
T
I
t
n
r
e
n
a
R
e
l
e
s
t
Low Voltage Reset Timing Chart
Note: tRSTD is power-on delay, typical time=100ms
Watchdog Time-out Reset during Normal Operation
●
The Watchdog time-out Reset during normal operation is the same as a hardware RES pin reset
except that the Watchdog time-out flag TO will be set to "1".
W
T
D
T
m
i
-
e
o
u
t
t
R
T
S
D
+
t
S
S
T
I
t
n
r
e
n
a
R
e
l
e
s
t
WDT Reset during Normal Operation Timing Chart
Note: tRSTD is power-on delay, typical time=100ms
Watchdog Time-out Reset during Idle/Sleep mode
●
The Watchdog time-out Reset during Idle/Sleep mode is a little different from other kinds of reset.
Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will
be cleared to "0" and the TO flag will be set to "1". Refer to the A.C. Characteristics for tSST details.
W
T
D
T
m
i
-
e
o
u
t
t
S
S
T
I
t
n
r
e
n
a
R
e
l
e
s
t
WDT Time-out Reset during Idle/Sleep Timing Chart
Note: The tSST can be chosen to be either 1024 or 2 clock cycles via configuration option if the system
clock source is provided by ERC or HIRC. The SST is 1024 for HXT or LXT.
Rev. 1.00
38
�anꢀaꢁꢂ ꢃꢄꢅ ꢃ011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
