HT46R068B/HT46R069B
Enhanced A/D Type 8-bit OTP MCU
Pin Description
Pin Name
Function
PA0
OPT
PAPU
PAWK
I/T
O/T
Descriptions
Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp and
wake-ꢀp.
ST CMOS
PA0/AN0
AN0
ANCSR0 AN
PAPU
PAWK
—
A/D channel 0
Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp and
wake-ꢀp.
PA1
ST CMOS
PA1/PFD/AN1
PAꢃ/TC0/ANꢃ/VREF
PA3/INTB/AN3
PFD
AN1
CTRL0
ANCSR0 AN
PAPU
PAWK
—
ANCSR0 AN
ACSR
PAPU
PAWK
—
ANCSR0 AN
PAPU
PAWK
CTRL0
—
—
CMOS PFD oꢀtpꢀt
—
A/D channel 1
Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp and
wake-ꢀp.
PAꢃ
ST CMOS
TC0
ANꢃ
VREF
ST
—
—
—
Exteꢁnal Timeꢁ 0 clock inpꢀt
A/D channel ꢃ
ADC ꢁefeꢁence inpꢀt
AN
Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp and
wake-ꢀp.
PA3
ST CMOS
INTB
AN3
ST
—
—
Exteꢁnal Inteꢁꢁꢀpt inpꢀt
A/D channel 3
Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp and
wake-ꢀp.
CMOS PWM oꢀtpꢀt
PA4
ST CMOS
PWM0
TC1
AUD
—
ST
—
PA4/PWM0/TC1/AUD
—
Exteꢁnal Timeꢁ 1 clock inpꢀt
—
AN DAC oꢀtpꢀt
PAPU
PAWK
CO
PAPU
PAWK
Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp and
wake-ꢀp.
OSC Oscillatoꢁ pin
PA5
OSCꢃ
PAꢄ
ST CMOS
PA5/OSCꢃ
PAꢄ/OSC1
—
Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp and
wake-ꢀp.
ST CMOS
OSC1
PA7
RES
PB0
SCOM0
PB1
SCOM1
PBꢃ
SCOMꢃ
PB3
SCOM3
PB4ꢅPB5
PBꢄ
SCSA
PB7
SCKA
PC0
AN4
PC1
AN5
PCꢃ
PWMꢃ
PC3
PWM1
PC4
XTꢃ
CO
PAWK
CO
OSC
—
Oscillatoꢁ pin
ST NMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled wake-ꢀp.
ST Reset inpꢀt
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp
SCOM Softwaꢁe contꢁolled 1/ꢃ bias LCD COM
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp
SCOM Softwaꢁe contꢁolled 1/ꢃ bias LCD COM
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp
SCOM Softwaꢁe contꢁolled 1/ꢃ bias LCD COM
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp
SCOM Softwaꢁe contꢁolled 1/ꢃ bias LCD COM
PA7/RES
—
PBPU
SCOMC
PBPU
SCOMC
PBPU
SCOMC
PBPU
SCOMC
PBPU
PBPU
—
PB0/SCOM0
PB1/SCOM1
PBꢃ/SCOMꢃ
—
—
—
PB3/SCOM3
PB4ꢅPB5
—
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp
ST
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp
ST CMOS SPI Seꢁial Clock
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp.
PBꢄ/SCSA
—
SPI Slave Select
PBPU
—
PCPU
PB7/SCKA
PC0/AN4
PC1/AN5
PCꢃ/PWMꢃ
PC3/PWM1
PC4/XTꢃ
ANCSR0 AN
PCPU ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp.
ANCSR0 AN A/D channel 5
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp.
CMOS PWM oꢀtpꢀt
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp.
CMOS PWM oꢀtpꢀt
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp.
LXT Low fꢁeqꢀencꢂ cꢁꢂstal pin
ST CMOS Geneꢁal pꢀꢁpose I/O. Registeꢁ enabled pꢀll-ꢀp.
LXT Low fꢁeqꢀencꢂ cꢁꢂstal pin
—
A/D channel 4
—
PCPU
CTRLꢃ
PCPU
CTRL0
PCPU
CO
—
—
—
PC5
XT1
PCPU
CO
PC5/XT1
—
Rev. 1.00
5
�anꢀaꢁꢂ ꢃꢄꢅ ꢃ011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
