HT46R064D/065D/066D
Enhanced A/D Type 8-Bit OTP MCU with LED Driver
Interrupts
Interrupts are an important part of any microcontroller system. When an external event or an internal
function such as a Timer/Event Counter or Time Base requires microcontroller attention, their
corresponding interrupt will enforce a temporary suspension of the main program allowing the
microcontroller to direct attention to their respective needs.
The devices contain a single external interrupt and multiple internal interrupts. The external interrupt
is controlled by the action of the external interrupt pin, while the internal interrupt is controlled by the
Timer/Event Counters and Time Base overflows.
Interrupt Register
Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by
using two registers, INTC0 and INTC1. By controlling the appropriate enable bits in this registers each
individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding
request flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all
interrupts.
Interrupt Operation
ATimer/Event Counter overflow, a Time Base event or an active edge on the external interrupt pin will
all generate an interrupt request by setting their corresponding request flag, if their appropriate
interrupt enable bit is set. When this happens, the Program Counter, which stores the address of the
next instruction to be executed, will be transferred onto the stack. The Program Counter will then be
loaded with a new address which will be the value of the corresponding interrupt vector. The
microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this
vector will usually be a JMP statement which will jump to another section of program which is known
as the interrupt service routine. Here is located the code to control the appropriate interrupt. The
interrupt service routine must be terminated with a RETI instruction, which retrieves the original
Program Counter address from the stack and allows the microcontroller to continue with normal
execution at the point where the interrupt occurred.
The various interrupt enable bits, together with their associated request flags, are shown in the
following diagram with their order of priority.
Interrupt Scheme
Rev. 1.00
65
January 12, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
