HT46R064D/065D/066D
Enhanced A/D Type 8-Bit OTP MCU with LED Driver
INTC1 Register - All devices
Bit
Name
R/W
7
6
5
4
3
2
1
0
TBF
R/W
0
ADF
R/W
0
TBE
R/W
0
ADE
R/W
0
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
POR
Bit 7~6
unimplemented, read as ²0²
Bit 5
Bit 4
TBF: Time Base event interrupt request flag
0: inactive
1: active
ADF: A/D Conversion interrupt request flag
0: inactive
1: active
Bit 3~2
Bit 1
unimplemented, read as ²0²
TBE: Time base event interrupt enable
0: disable
1: enable
Bit 0
ADE: A/D Conversion interrupt enable
0: disable
1: enable
Timer/Event Counter Interrupt
For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the
corresponding timer interrupt enable bit, TnE, must first be set. An actual Timer/Event Counter
interrupt will take place when the Timer/Event Counter request flag, TnF, is set, a situation that will
occur when the relevant Timer/Event Counter overflows. When the interrupt is enabled, the stack is
not full and a Timer/Event Counter n overflow occurs, a subroutine call to the relevant timer interrupt
vector, will take place. When the interrupt is serviced, the timer interrupt request flag, TnF, will be
automatically reset and the EMI bit will be automatically cleared to disable other interrupts.
Time Base Interrupt
For a time base interrupt to occur the global interrupt enable bit EMI and the corresponding interrupt
enable bit TBE, must first be set. An actual Time Base interrupt will take place when the time base
request flag TBF is set, a situation that will occur when the Time Base overflows. When the interrupt is
enabled, the stack is not full and a time base overflow occurs a subroutine call to time base vector will
take place. When the interrupt is serviced, the time base interrupt flag. TBF will be automatically reset
and the EMI bit will be automatically cleared to disable other interrupts.
Programming Considerations
By disabling the interrupt enable bits, a requested interrupt can be prevented from being serviced,
however, once an interrupt request flag is set, it will remain in this condition in the interrupt register
until the corresponding interrupt is serviced or until the request flag is cleared by a software
instruction.
It is recommended that programs do not use the ²CALL subroutine² instruction within the interrupt
subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in
some applications. If only one stack is left and the interrupt is not well controlled, the original control
sequence will be damaged once a ²CALL subroutine² is executed in the interrupt subroutine.
All of these interrupts have the capability of waking up the processor when in the Sleep Mode.
Rev. 1.00
69
January 12, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
