HT46R064D/065D/066D
Enhanced A/D Type 8-Bit OTP MCU with LED Driver
Step 6
To check when the analog to digital conversion process is complete, the EOCB bit in the ADCR
register can be polled. The conversion process is complete when this bit goes low. When this occurs
the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an
alternative method if the interrupts are enabled and the stack is not full, the program can wait for an
A/D interrupt to occur.
Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the
ADCR register is used, the interrupt enable step above can be omitted.
The accompanying diagram shows graphically the various stages involved in an analog to digital
conversion process and its associated timing.
The setting up and operation of the A/D converter function is fully under the control of the application
program as there are no configuration options associated with the A/D converter. After an A/D
conversion process has been initiated by the application program, the microcontroller internal hardware
will begin to carry out the conversion, during which time the program can continue with other functions.
The time taken for the A/D conversion is 16tAD where tAD is equal to the A/D clock period.
Programming Considerations
When programming, special attention must be given to the PCR[7:0] bits in the register. If these bits
are all cleared to zero no external pins will be selected for use as A/D input pins allowing the pins to be
used as normal I/O pins. When this happens the internal A/D circuitry will be power down.
A/D Transfer Function
As the device contain a 12-bit A/D converter, its full-scale converted digitised value is equal to FFFH.
Since the full-scale analog input value is equal to the VDD voltage, this gives a single bit analog input
value of VDD/4096. The diagram show the ideal transfer function between the analog input value and
the digitised output value for the A/D converter.
Note that to reduce the quantisation error, a 0.5 LSB offset is added to the A/D Converter input. Except
for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below
where they would change without the offset, and the last full scale digitised value will change at a point
1.5 LSB below the VDD level.
Rev. 1.00
62
January 12, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
