HT46R064D/065D/066D
Enhanced A/D Type 8-Bit OTP MCU with LED Driver
Interrupt Priority
Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be
serviced on the latter of the two T2 pulses, if the corresponding interrupts are enabled. In case of
simultaneous requests, the following table shows the priority that is applied. These can be masked by
resetting the EMI bit.
HT46R064D
Interrupt Source
Priority
Vector
04H
External Interrupt
1
2
3
4
Timer/Event Counter 0 Overflow
A/D Conversion Complete
Time Base Overflow
08H
10H
14H
HT46R065D/HT46R066D
Interrupt Source
Priority
Vector
04H
External Interrupt
1
Timer/Event Counter 0 Overflow
Timer/Event Counter 1 Overflow
A/D Conversion Complete
Time Base Overflow
2
3
4
5
08H
0CH
10H
14H
In cases where both external and internal interrupts are enabled and where an external and internal in-
terrupt occurs simultaneously, the external interrupt will always have priority and will therefore be
serviced first. Suitable masking of the individual interrupts using the interrupt registers can prevent
simultaneous occurrences.
External Interrupt
For an external interrupt to occur, the global interrupt enable bit, EMI, and external interrupt enable bit,
INTE, must first be set. An actual external interrupt will take place when the external interrupt request
flag, INTF, is set, a situation that will occur when an edge transition appears on the external INT line.
The type of transition that will trigger an external interrupt, whether high to low, low to high or both is
determined by the INTEG0 and INTEG1 bits, which are bits 6 and 7 respectively, in the CTRL1
control register. These two bits can also disable the external interrupt function.
INTEG1
INTEG0
Edge Trigger Type
External interrupt disable
0
0
1
1
0
1
0
1
Rising edge Trigger
Falling edge Trigger
Both edge Trigger
The external interrupt pin is pin-shared with the I/O pin PA0 and can only be configured as an exter-
nal interrupt pin if the corresponding external interrupt enable bit in the INTC0 register has been set
and the edge trigger type has been selected using the CTRL1 register. The pin must also be setup as
an input by setting the corresponding PAC.0 bit in the port control register. When the interrupt is en-
abled, the stack is not full and a transition appears on the external interrupt pin, a subroutine call to
the external interrupt vector at location 04H, will take place. When the interrupt is serviced, the exter-
nal interrupt request flag, INTF, will be automatically reset and the EMI bit will be automatically
Rev. 1.00
67
January 12, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
