HT46RU66/HT46CU66
-
¨
Receiver interrupt
No interrupt will be generated. However this bit
rises at the same time as the RXIF bit which itself
generates an interrupt.
The read only receive interrupt flag RXIF in the USR
register is set by an edge generated by the receiver.
An interrupt is generated if RIE=1, when a word is
transferred from the Receive Shift Register, RSR, to
the Receive Data Register, RXR. An overrun error
can also generate an interrupt if RIE=1.
Note that the NF flag is reset by a USR register read
operation followed by an RXR register read
operation.
¨
Framing Error - FERR Flag
The read only framing error flag, FERR, in the USR
register, is set if a zero is detected instead of stop
bits. If two stop bits are selected, both stop bits must
be high, otherwise the FERR flag will be set. The
FERR flag is buffered along with the received data
and is cleared on any reset.
·
Managing receiver errors
Several types of reception errors can occur within the
UART module, the following section describes the
various types and how they are managed by the
UART.
¨
Overrun Error - OERR flag
¨
Parity Error - PERR Flag
The RXR register is composed of a two byte deep
FIFO data buffer, where two bytes can be held in the
FIFO register, while a third byte can continue to be
received. Before this third byte has been entirely
shifted in, the data should be read from the RXR
register. If this is not done, the overrun error flag
OERR will be consequently indicated.
The read only parity error flag, PERR, in the USR
register, is set if the parity of the received word is in-
correct. This error flag is only applicable if the parity
is enabled, PREN = 1, and if the parity type, odd or
even is selected. The read only PERR flag is buf-
fered along with the received data bytes. It is
cleared on any reset. It should be noted that the
FERR and PERR flags are buffered along with the
corresponding word and should be read before
reading the data word.
In the event of an overrun error occurring, the fol-
lowing will happen:
-
The OERR flag in the USR register will be set.
-
The RXR contents will not be lost.
·
UART interrupt scheme
-
The shift register will be overwritten.
The UART internal function possesses its own inter-
nal interrupt and independent interrupt vector. Several
individual UART conditions can generate an internal
UART interrupt. These conditions are, a transmitter
data register empty, transmitter idle, receiver data
available, receiver overrun, address detect and an RX
pin wake-up. When any of these conditions are cre-
ated, if the UART interrupt is enabled and the stack is
not full, the program will jump to the UART interrupt
vector where it can be serviced before returning to the
main program. Four of these conditions, have a corre-
sponding USR register flag, which will generate a
UART interrupt if its associated interrupt enable flag in
-
An interrupt will be generated if the RIE bit is set.
The OERR flag can be cleared by an access to the
USR register followed by a read to the RXR register.
¨
Noise Error - NF Flag
Over-sampling is used for data recovery to identify
valid incoming data and noise. If noise is detected
within a frame the following will occur:
-
The read only noise flag, NF, in the USR register
will be set on the rising edge of the RXIF bit.
-
Data will be transferred from the Shift register to
the RXR register.
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UART Interrupt Scheme
Rev. 1.20
43
October 2, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
