HT46R47-H
Example: using interrupt method to detect end of conversion
clr
mov
mov
EADI
a,00000001B
ACSR,a
; disable ADC interrupt
; setup the ACSR register to select fSYS/8 as the A/D clock
mov
mov
a,00100000B
ADCR,a
:
; setup ADCR register to configure Port PB0~PB3 as A/D inputs
; and select AN0 to be connected to the A/D converter
; As the Port B channel bits have changed the following START
; signal (0-1-0) must be issued within 10 instruction cycles
:
Start_conversion:
clr
set
clr
START
START
START
ADF
; reset A/D
; start A/D
clr
; clear ADC interrupt request flag
; enable ADC interrupt
; enable global interrupt
set
set
EADI
EMI
:
:
:
; ADC interrupt service routine
ADC_ISR:
mov
mov
mov
acc_stack,a
a,STATUS
status_stack,a
:
; save ACC to user defined memory
; save STATUS to user defined memory
:
mov
mov
mov
mov
clr
a,ADRH
adrh_buffer,a
a,ADRL
adrl_buffer,a
START
START
START
:
; read conversion result high byte value from the ADRH register
; save result to user defined register
; read conversion result low byte value from the ADRL register
; save result to user defined register
set
clr
; reset A/D
; start A/D
:
EXIT_INT_ISR:
mov
mov
mov
reti
a,status_stack
STATUS,a
a,acc_stack
; restore STATUS from user defined memory
; restore ACC from user defined memory
Low Voltage Reset - LVR
The relationship between VDD and VLVR is shown below.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~3.3V, such as changing a battery, the LVR will au-
tomatically reset the device internally.
V
D
D
V
O P R
5
.
5
V
5
.
5
V
V
L
V
R
The LVR includes the following specifications:
3
.
0
V
·
The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
2
.
2
V
0
.
9
V
·
The LVR uses the ²OR² function with the external RES
signal to perform chip reset.
Note:
V
OPR is the voltage range for proper chip
operation at 4MHz system clock.
Rev. 1.30
20
March 1, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
