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HT46R47-H(18SOP) 参数 Datasheet PDF下载

HT46R47-H(18SOP)图片预览
型号: HT46R47-H(18SOP)
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 8-Bit, UVPROM, 8MHz, CMOS, PDSO18]
分类和应用: 可编程只读存储器LTE微控制器光电二极管
文件页数/大小: 42 页 / 296 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
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HT46R47-H  
Bit No.  
Label  
Function  
ACS2, ACS1, ACS0: Select A/D channel  
0, 0, 0: AN0  
0
1
2
ACS0  
ACS1  
ACS2  
0, 0, 1: AN1  
0, 1, 0: AN2  
0, 1, 1: AN3  
1, X, X: undefined, cannot be used  
PCR2, PCR1, PCR0: PB3~PB0 configurations  
0, 0, 0: PB3 PB2 PB1 PB0 (The ADC circuit is power off to reduce power consumption.)  
0, 0, 1: PB3 PB2 PB1 AN0  
3
4
5
PCR0  
PCR1  
PCR2  
0, 1, 0: PB3 PB2 AN1 AN0  
0, 1, 1: PB3 AN2 AN1 AN0  
1, x, x: AN3 AN2 AN1 AN0  
Indicates end of A/D conversion. (0 = end of A/D conversion)  
Each time bits 3~5 change state the A/D should be initialized by issuing a START signal,  
otherwise the EOCB flag may have an undefined condition. See ²Important note for A/D ini-  
tialization².  
6
7
EOCB  
Start the A/D conversion  
START 0®1®0= Start  
0®1= Reset A/D converter and set EOCB to ²1²  
ADCR (22H) Register  
Bit No.  
Label  
Function  
Select the A/D converter clock source.  
0, 0: fSYS/2  
0
1
ADCS0  
ADCS1  
0, 1: fSYS/8  
1, 0: fSYS/32  
1, 1: Undefined  
2~6  
7
¾
Unused bit, read as ²0².  
TEST  
For internal test only.  
ACSR (23H) Register  
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first exam-  
ple, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,  
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.  
Example: using EOCB Polling Method to detect end of conversion  
clr  
EADI  
a,00000001B  
ACSR,a  
a,00100000B  
ADCR,a  
; disable ADC interrupt  
mov  
mov  
mov  
mov  
; setup the ACSR register to select fSYS/8 as the A/D clock  
; setup ADCR register to configure Port PB0~PB3 as A/D inputs  
; and select AN0 to be connected to the A/D converter  
:
:
; As the Port B channel bits have changed the following START  
; signal (0-1-0) must be issued within 10 instruction cycles  
:
Start_conversion:  
clr  
set  
clr  
START  
START  
START  
; reset A/D  
; start A/D  
Polling_EOC:  
sz  
EOCB  
; poll the ADCR register EOCB bit to detect end of A/D conversion  
; continue polling  
; read conversion result high byte value from the ADRH register  
; save result to user defined memory  
; read conversion result low byte value from the ADRL register  
; save result to user defined memory  
jmp  
mov  
mov  
mov  
mov  
polling_EOC  
a,ADRH  
adrh_buffer,a  
a,ADRL  
adrl_buffer,a  
:
:
start_conversion  
jmp  
; start next A/D conversion  
19  
Rev. 1.30  
March 1, 2006  
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