HT46R47-H
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of four
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled, and the
A/D converter circuit is power on. The EOCB bit (bit6 of
the ADCR) is end of A/D conversion flag. Check this bit
to know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of A/D
converter. Give START bit a raising edge and falling
edge that means the A/D conversion has started. In or-
der to ensure the A/D conversion is completed, the
START should stay at ²0² until the EOCB is cleared to
²0² (end of A/D conversion).
Bit 7 of the ACSR register is used for test purposes only
and must not be used for other purposes by the applica-
tion program. Bit1 and bit0 of the ACSR register are
used to select the A/D clock source.
When the A/D conversion has completed, the A/D inter-
rupt request flag will be set. The EOCB bit is set to ²1²
when the START bit is set from ²0² to ²1².
Important Note for A/D initialization:
Special care must be taken to initialize the A/D con-
verter each time the Port B A/D channel selection bits
are modified, otherwise the EOCB flag may be in an un-
defined condition. An A/D initialization is implemented
by setting the START bit high and then clearing it to zero
within 10 instruction cycles of the Port B channel selec-
tion bits being modified. Note that if the Port B channel
selection bits are all cleared to zero then an A/D initial-
ization is not required.
Register
ADRL
Bit7
D0
Bit6
¾
Bit5
¾
Bit4
¾
Bit3
¾
Bit2
¾
Bit1
¾
Bit0
¾
ADRH
D8
D7
D6
D5
D4
D3
D2
D1
Note: D0~D8 is A/D conversion result data bit LSB~MSB.
ADRL (20H), ADRH (21H) Register
M
i
n
i
m
u
m
o
n
e
i
n
s
t
r
u
c
t
i
o
n
c
y
c
l
e
n
e
e
d
e
d
,
M
a
x
i
m
u
m
t
e
n
i
n
s
t
r
u
c
t
i
o
n
c
y
c
l
e
s
a
l
l
o
w
e
d
S
T
A
R
T
E
O
C
B
A
/
D
s
a
m
p
l
i
n
g
t
i
m
e
A
/
D
s
a
m
p
l
i
n
g
t
i
m
e
A
/
D
s
a
m
p
l
i
n
g
t
i
m
e
t
A
D
C
S
1
t
A
D
C
S
1
t
A
D
C
S
1
P
C
R
2
~
0
0
0
B
1
0
0
B
1
0
1
B
0
0
0
B
1
0
0
B
P
C
R
0
1
.
P
A
t
B
p
o
r
t
s
e
t
u
p
a
s
I
/
O
s
2
.
/
D
c
o
n
v
e
r
t
e
r
i
s
p
o
w
e
r
e
d
o
f
f
o
r
e
d
u
c
e
p
o
w
e
r
c
o
n
s
u
m
p
t
i
o
n
A
C
S
2
~
d
o
n
'
t
c
a
r
e
0
0
0
B
0
0
0
B
0
0
1
B
0
1
0
B
A
C
S
0
P
o
w
e
r
-
o
n
S
t
a
r
t
o
f
A
/
D
S
t
a
r
t
o
f
A
/
D
S
t
a
r
t
o
f
A
/
D
R
e
s
e
t
c
o
n
v
e
r
s
i
o
n
c
o
n
v
e
r
s
i
o
n
c
o
n
v
e
r
s
i
o
n
R
e
s
e
t
A
/
D
R
e
s
e
t
A
/
D
R
e
s
e
t
A
/
D
c
o
n
v
e
r
t
e
r
c
o
n
v
e
r
t
e
r
c
o
n
v
e
r
t
e
r
E
n
d
o
f
A
/
D
E
n
d
o
f
A
/
D
E
n
d
o
f
A
/
D
c
o
n
v
e
r
s
i
o
n
c
o
n
v
e
r
s
i
o
n
c
o
n
v
e
r
s
i
o
n
1
:
D
e
f
i
n
e
P
B
c
o
n
f
i
g
u
r
a
t
i
o
n
2
:
S
e
l
e
c
t
a
n
a
l
o
g
c
h
a
n
n
e
l
t
A
D
C
1
t
A
D
C
1
t
A D C 1
A
/
D
c
o
n
v
e
r
s
i
o
n
t
i
m
e
A
/
D
c
o
n
v
e
r
s
i
o
n
t
i
m
e
A
/
D
c
o
n
v
e
r
s
i
o
n
t
i
m
e
N
o
t
e
:
A
t
t
S
Y
S
S
Y
S
S
Y
S
A
A
D
D
C
C
S
1
1
=
3
2
t
A
D
D
=
7
6
t
A/D Conversion Timing
Rev. 1.30
18
March 1, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
