HT46R12
Options
The following shows ten kinds of options in the microcontroller. ALL the options must be defined to ensure proper sys-
tem function.
Options
OSC type selection.
This option is to determine if an RC or crystal oscillator is chosen as system clock.
WDT source selection.
There are three types of selection: On-chip RC oscillator, instruction clock or disable the WDT.
CLRWDT times selection.
This option defines how to clear the WDT by instruction. ²One time² means that the ²CLR WDT² instruction can clear
the WDT. ²Two times² means only if both of the ²CLR WDT1² and ²CLR WDT2² instructions have been executed,
then WDT can be cleared.
WDT time-out period selection.
There are four types of selection: fS/213, fS/214, fS/215 and fS/216
Wake-up selection.
This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up the
chip from a HALT.
Pull-high selection.
This option is to determine whether a pull-high resistance is viable or not in the input mode of the I/O ports. PA0~PA7,
can be independently selected.
Pull-high selection.
This option is to decide whether a pull-high resistance is viable or not in the input mode of the I/O ports. PB0~PB3,
can be independently selected
Pull-high selection.
This option is to determine whether a pull-high resistance is viable or not in the input mode of the I/O ports.
PC0~PC3, can be independently selected
I/O pins share with other function selections.
PA3/PFD: PA3 can be set as I/O pins or PFD output.
PFD selection.
If PA3 is set as PFD output, there are two types of selections; One is PFD0 as the PFD output, the other is PFD1 as
the PFD output. PFD0, PFD1 are generated by the timer overflow signals of the Timer/Event Counter 0, Timer/Event
Counter 1 respectively.
Low voltage reset selection.
Enable or disable LVR function.
PPG0 output level selection; P0LEV.
This option is to determine the PPG output level. Active Low or Active High selection. Disable this bit to ²0², the PPG
output will be defined as an active high output, Enable this bit to ²1², the PPG output will be defined as an active low
output
PPG0 timer start counting synchronized with clock; P0TSYN.
This option is to determine the PPG0 timer start counting is synchronized with input clock or not.
Rev. 1.20
24
February 24, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
