HT46R01/HT46R02/HT46R03
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INTC1 Register - HT46R02/HT46R03
Interrupt Operation
The various interrupt enable bits, together with their as-
sociated request flags, are shown in the following dia-
gram with their order of priority.
A Timer/Event Counter overflow, an end of A/D conver-
sion or an active edge on the external interrupt pin will all
generate an interrupt request by setting their corre-
sponding request flag, if their appropriate interrupt en-
able bit is set. When this happens, the Program
Counter, which stores the address of the next instruction
to be executed, will be transferred onto the stack. The
Program Counter will then be loaded with a new ad-
dress which will be the value of the corresponding inter-
rupt vector. The microcontroller will then fetch its next
instruction from this interrupt vector. The instruction at
this vector will usually be a JMP statement which will
jump to another section of program which is known as
the interrupt service routine. Here is located the code to
control the appropriate interrupt. The interrupt service
routine must be terminated with a RETI statement,
which retrieves the original Program Counter address
from the stack and allows the microcontroller to continue
with normal execution at the point where the interrupt
occurred.
Once an interrupt subroutine is serviced, all the other in-
terrupts will be blocked, as the EMI bit will be cleared au-
tomatically. This will prevent any further interrupt nesting
from occurring. However, if other interrupt requests oc-
cur during this interval, although the interrupt will not be
immediately serviced, the request flag will still be re-
corded. If an interrupt requires immediate servicing
while the program is already in another interrupt service
routine, the EMI bit should be set after entering the rou-
tine, to allow interrupt nesting. If the stack is full, the in-
terrupt request will not be acknowledged, even if the
related interrupt is enabled, until the Stack Pointer is
decremented. If immediate service is desired, the stack
must be prevented from becoming full.
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A
D
F
Interrupt Scheme
Note: In the figure, the T1F interrupt request flag and the ET1I interrupt enable bit only exist for the
HT46R02/HT46R03 devices, which have two timers.
Rev. 1.00
34
September 21, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
