HT46R01/HT46R02/HT46R03
Timer/Event Counter Interrupt
Interrupt Priority
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding inter-
rupts are enabled. In case of simultaneous requests,
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
For a Timer/Event Counter interrupt to occur, the global
interrupt enable bit, EMI, and the corresponding timer
interrupt enable bit, ET0I or ET1I, must first be set. An
actual Timer/Event Counter interrupt will take place
when the Timer/Event Counter request flag, T0F or T1F,
is set, a situation that will occur when the relevant
Timer/Event Counter overflows. When the interrupt is
enabled, the stack is not full and a Timer/Event Counter
0 overflow occurs, a subroutine call to the timer interrupt
vector at location 08H, will take place. For those devices
with two timers, the Timer/Event Counter 1 overflow has
an interrupt vector at location 0CH. When the interrupt is
serviced, the timer interrupt request flag, T0F or T1F, will
be automatically reset and the EMI bit will be automati-
cally cleared to disable other interrupts.
HT46R02
Interrupt Source
HT46R01
HT46R03
External Interrupt
1
2
1
Timer/Event Counter 0
Overflow
2
Timer/Event Counter 1
Overflow
N/A
3
3
4
A/D Converter Interrupt
In cases where both external and internal interrupts are
enabled and where an external and internal interrupt oc-
curs simultaneously, the external interrupt will always
have priority and will therefore be serviced first. Suitable
masking of the individual interrupts using the interrupt
registers can prevent simultaneous occurrences.
A/D Interrupt
For an A/D interrupt to occur, the global interrupt enable
bit, EMI, and the corresponding interrupt enable bit,
EADI, must be first set. An actual A/D interrupt will take
place when the A/D converter request flag, ADF, is set, a
situation that will occur when an A/D conversion process
has completed. When the interrupt is enabled, the stack
is not full and an A/D conversion process finishes exe-
cution, a subroutine call to the A/D interrupt vector at lo-
cation 0CH for the HT46R01 devices or 10H for the
other devices, will take place. When the interrupt is ser-
viced, the A/D interrupt request flag, ADF, will be auto-
matically reset and the EMI bit will be automatically
cleared to disable other interrupts.
External Interrupt
For an external interrupt to occur, the global interrupt en-
able bit, EEI, and external interrupt enable bit, EEI, must
first be set. An actual external interrupt will take place
when the external interrupt request flag, EIF, is set, a sit-
uation that will occur when an edge transition appears
on the externalINTline. The type of transition that will
trigger an external interrupt, whether high to low, low to
high or both is determined by the INTES0 and INTES1
bits, which are bits 6 and 7 respectively, in the CTRL1
control register. These two bits can also disable the ex-
ternal interrupt function.
Programming Considerations
By disabling the interrupt enable bits, a requested inter-
rupt can be prevented from being serviced, however,
once an interrupt request flag is set, it will remain in this
condition in the interrupt register until the corresponding
interrupt is serviced or until the request flag is cleared by
a software instruction.
INTES1
INTES0
Edge Trigger Type
Disable
0
0
1
1
0
1
0
1
Rising Edge Trigger
Falling Edge Trigger
Dual Edge Trigger
It is recommended that programs do not use the ²CALL
subroutine² instruction within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and the interrupt is not well con-
trolled, the original control sequence will be damaged
once a ²CALL subroutine² is executed in the interrupt
subroutine.
The external interrupt pin is pin-shared with the I/O pin
PA3 and can only be configured as an external interrupt
pin if the corresponding external interrupt enable bit in
the INTC0 register has been set and the edge trigger
type has been selected using the CTRL1 register. The
pin must also be setup as an input by setting the corre-
sponding PAC.3 bit in the port control register. When the
interrupt is enabled, the stack is not full and a transition
appears on the external interrupt pin, a subroutine call to
the external interrupt vector at location 04H, will take
place. When the interrupt is serviced, the external inter-
rupt request flag, EIF, will be automatically reset and the
EMI bit will be automatically cleared to disable other in-
terrupts. Note that any pull-high resistor connections on
this pin will remain valid even if the pin is used as an ex-
ternal interrupt input.
All of these interrupts have the capability of waking up
the processor when in the Power Down Mode.
Only the Program Counter is pushed onto the stack. If
the contents of the register or status register are altered
by the interrupt service program, which may corrupt the
desired control sequence, then the contents should be
saved in advance.
Rev. 1.00
35
September 21, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
