HT46R01/HT46R02/HT46R03
In addition, on entering an interrupt sequence or execut-
ing a subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status registers are important and if the interrupt rou-
tine can change the status register, precautions must be
taken to correctly save it.
Pulse Width Modulation Register - PWM
Each device contains a Pulse Width Modulator which
has a corresponding control register, known as PWM.
The 8-bit contents of this register defines the duty cycle
value for the modulation cycle of the Pulse Width Modu-
lator.
Interrupt Control Registers - INTC0,INTC1
A/D Converter Registers - ADR, ADRL, ADRH,
ADCR, ACSR
These 8-bit registers, known as INTC0 and INTC1, con-
trol the operation of both external, and internal timer and
A/D interrupts. By setting various bits within this register
using standard bit manipulation instructions, the en-
able/disable function of each interrupt can be independ-
ently controlled. A master interrupt bit within this
register, the EMI bit, acts like a global enable/disable
and is used to set all of the interrupt enable bits on or off.
This bit is cleared when an interrupt routine is entered to
disable further interrupt and is set by executing the
²RETI² instruction. Note that the INTC1 register does
not exist on the HT46R01 devices.
Each device contains a 4-channel 8-bit, 9-bit or 12-bit
A/D converter. The correct operation of the A/D requires
the use of one or two data registers, a control register
and a clock source register. For the HT46R01 devices,
which have an 8-bit A/D converter, there is a single data
register, known as ADR. For the other devices, which
contain higher resolution A/D converters, there are two
data registers, a high byte data register known as
ADRH, and a low byte data register known as ADRL.
These are the register locations where the digital value
is placed after the completion of an analog to digital con-
version cycle. The channel selection and configuration
of the A/D converter is setup via the control register
ADCR while the A/D clock frequency is defined by the
clock source register, ACSR.
Timer/Event Counter Registers
Depending upon which device is selected, all devices
contain one or two integrated 8-bit Timer/Event Coun-
ters. For the HT46R01 devices, which have a single
8-bit Timer/Event Counter, an associated register
known as TMR0 is the location where the timer¢s 8-bit
value is located. An associated control register, known
as TMR0C, contains the setup information for this timer.
As the HT46R02 and HT46R03 devices contain two
8-bit Timer/Event Counters and additional register pair
exists, with the names TMR1 and TMR1C.
System Control Register - CTRL0
This register is used to provide control over certain inter-
nal functions including certain system clock options, the
PFD clock source and on/off control, the PWM mode
and on/off control and an RTC Oscillator quick start up
function.
System Control Register - CTRL1
Input/Output Ports and Control Registers
This register is used to provide control over certain inter-
nal functions including the External Interrupt edge trig-
ger type and the Watchdog Timer control function.
Within the area of Special Function Registers, the port
PA data I/O register and its associated control register
PAC play a prominent role. These registers are mapped
to specific addresses within the Data Memory as shown
in the Data Memory table. The PA data I/O register, is
used to transfer the appropriate output or input data on
the PA port. The PAC control register specifies which
pins of PA are set as inputs and which are set as out-
puts. To setup a pin as an input, the corresponding bit of
the control register must be set high, for an output it
must be set low. During program initialisation, it is impor-
tant to first setup the control registers to specify which
pins are outputs and which are inputs before reading
data from or writing data to the I/O ports. One flexible
feature of these registers is the ability to directly pro-
gram single bits using the ²SET [m].i² and ²CLR [m].i²
instructions. The ability to change I/O pins from output to
input and vice versa by manipulating specific bits of the
I/O control registers during normal program operation is
a useful feature of these devices.
Wake-up Function Register - PAWK
When the microcontroller enters the Power Down Mode,
various methods exist to wake the device up and con-
tinue with normal operation. One method is to allow a
low going edge on the I/O pins to have a wake-up func-
tion. This register is used to select which I/O pins are
used to have this wake-up function.
Pull-high Register - PAPU
The I/O pins, if configured as inputs, can have internal
pull-high resistors connected, which eliminates the need
for external pull-high resistors. This register selects which
I/O pins are connected to internal pull-high resistors.
Rev. 1.00
14
September 21, 2007
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
