HT46F46E/HT46F47E/HT46F48E/HT46F49E
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ERASE Timing - Except HT46F49E
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ERASE Timing - HT46F49E
Internal Write Cycle
high the DO bit will go low to indicated that the write cycle
is in progress. When the DO bit returns high this indicates
that the internal write cycle has ended and that the
EEPROM is ready to receive further instructions.
The write or erase instructions, ²WRITE², ²ERASE²,
²ERAL² or ²WRAL² will all use the EEPROM¢s internal
write cycle function. As this function is completely inter-
nally timed, the SK clock is not required. As the MCU has
no control over the timing of this write cycle, it must still
have some way of knowing when the internal write cycle
has completed. This is because, when the internal write
cycle is executing, the EEPROM will not accept any fur-
ther instructions from the MCU. The MCU must therefore
wait until the write cycle has finished before sending any
further instructions.
Initialising the EEPROM
After the MCU is powered on and if the EEPROM is to
be used, it must be initialised in a specific way before
any user instructions are transmitted. This is achieved
by first transmitting an EWEN instruction, then by issu-
ing a WRITE instruction to write random data to any sin-
gle address in the EEPROM. The initialisation
procedure can then be terminated by issuing an EWDS
instruction, however at this point, if actual user data is to
be imminently written to the EEPROM, this last step is
optional.
One way for the MCU to know when the write cycle has
terminated is to poll the DO bit after the CS bit has issued
a low pulse. The low going edge of this CS bit pulse will
initiate the internal write cycle, when the bit is returned
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Internal Write Cycle Busy Polling
Rev. 1.40
24
July 28, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
