HT46F46E/HT46F47E/HT46F48E/HT46F49E
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ERAL Timing
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WRAL Timing
any previously written data making it unnecessary to
first issue an erase instruction.
ended. Before an ²ERAL² instruction is transmitted an
²EWEN² instruction must have been transmitted at
some point earlier to ensure that the erase/write function
of the EEPROM is enabled.
ERASE
The ²ERASE² instruction is used to erase data at a
specified addresses. The data at the address specified
will be set to ²1². To instigate an ²ERASE² instruction,
the CS bit should be set high, followed by a high start bit
and then the instruction code ²11², all transmitted via the
DI bit. The address information should then follow with
the MSB bit being transmitted first. For the HT46F49E
device, a dummy bit must be inserted between the last
bit of the instruction code and the MSB of the address.
After all the ²ERASE² instruction code and address
have been transmitted, the data at the specified address
will be erased when the CS bit is cleared to zero. The
EEPROM does this by executing an internal write cycle
which will set all data at the specified address to ²1².
This process takes place internally using the
EEPROM¢s own internal clock and does not require any
action from the SK clock. No further instructions can be
accepted by the EEPROM until the write cycle has fin-
ished. To determine when the write cycle has ended, the
CS should be again brought high and the DO bit polled.
If the DO bit is low this indicates that the write-cycle is
still in progress, however, the DO bit will change to a
high value when the write-cycle has ended. Before an
²ERASE² instruction is transmitted, an ²EWEN² instruc-
tion must have been transmitted at some point earlier to
ensure that the erase/write function of the EEPROM is
enabled.
WRAL
The WRAL instruction is used to write the same data
into the entire EEPROM. To instigate this instruction, the
CS bit should be set high, followed by a high start bit and
then the instruction code ²00². Following on from this, a
²01² should then be transmitted, and depending on
whether the internal EEPROM has a 128´8 or 256´8
capacity, this should be followed by either 5-bits or 7-bits
respectively, of ²don¢t-care² data. The data information
should then follow with the MSB bit being transmitted
first. After the instruction code and data have been
transmitted, the data will be written into the EEPROM
when the CS bit is cleared to zero. The EEPROM does
this by executing an internal write-cycle. This process
takes place internally using the EEPROM¢s own internal
clock and does not require any action from the SK clock.
No further instructions can be accepted by the
EEPROM until this internal write-cycle has finished. To
determine when the write cycle has ended, CS should
be again brought high and the DO bit polled. If D0 is low
this indicates that the internal write-cycle is still in prog-
ress, however the D0 bit will change to a high value
when the internal write-cycle has ended. Before a
²WRAL² instruction is transmitted an ²EWEN² instruc-
tion must have been transmitted at some point earlier to
ensure that the erase/write function of the EEPROM is
enabled. The WRAL instruction will automatically erase
Rev. 1.40
23
July 28, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
