HT46F46E/HT46F47E/HT46F48E/HT46F49E
t
C
D
S
V
e
r
i
S
f
y
t
a
n
d
b
y
C
S
S
K
D
I
1
0
1
A
6
A
5
A
4
A
1
A
0
D
7
D
0
S
t
a
r
t
b
i
t
t
S
V
B
u
s
y
D
O
P
t
R
WRITE Timing - Except HT46F49E
t
C
D
S
C
S
V
e
r
i
S
f
y
t
a
n
d
b
y
S
K
D
I
1
0
1
A
7
A
1
A
0
D
7
D
0
S
t
a
r
t
b
i
t
t
S
V
B
u
s
y
D
O
P
t
R
WRITE Timing - HT46F49E
C
S
S
t
a
n
d
b
y
S
K
D
I
1
0
0
E
W
W
E
N
=
1
1
S
t
a
r
t
b
i
t
X
X
´
8
X
X
E
X
E
P
-
R
-
O
5
M
-
b
i
t
f
o
r
1
E
D
S
X
=
X
0
X
0
X
X
X
X
´
-
8
-
E
7
E
-
P
b
i
R
t
O
M
f
o
r
2
5
6
EWEN/EWDS Timing
EWEN/EWDS
ERAL
The ²EWEN² instruction is the Erase/Write Enable in-
struction and the ²EWDS² instruction is the Erase/Write
Disable instruction. To instigate an ²EWEN² or ²EWDS²
instruction, the CS bit should first be set high, followed
by a high start bit and then the instruction code ²00². For
the ²EWEN² instruction, a ²11² should then be transmit-
ted and for the ²EWDS² instruction a ²00² should be
transmitted. Following on from this, and depending on
whether the internal EEPROM has a 128´8 or 256´8
capacity, either 5-bits or 7-bits respectively, of
²don¢t-care² data should then be transmitted to com-
plete the instruction. If the device is already in the Erase
Write Disable mode then no write or erase operations
can be executed thus protecting the internal EEPROM
data. Before any write or erase instruction is executed
an ²EWEN² instruction must be issued. After the
²EWEN² instruction is executed, the device will remain
in the Erase Write Enable mode until a subsequent
²EWDS² instruction is issued or until the device is pow-
ered down.
The ²ERAL² instruction is used to erase the whole con-
tents of the EEPROM memory. After it has been exe-
cuted all the data in the EEPROM will be set to ²1². To
instigate this instruction, the CS bit should be set high,
followed by a high start bit and then the instruction code
²00². Following on from this, a ²10² should then be
transmitted, and depending on whether the internal
EEPROM has a 128´8 or 256´8 capacity, this should be
followed by either 5-bits or 7-bits respectively, of
²don¢t-care² data to complete the instruction. After the
²ERAL² instruction code has been transmitted, the
EEPROM data will be erased when the CS bit is cleared
to zero. The EEPROM does this by executing an inter-
nal write-cycle. This process takes place internally using
the EEPROM¢s own internal clock and does not require
any action from the SK clock. No further instructions can
be accepted by the EEPROM until this internal write-cy-
cle has finished. To determine when the write cycle has
ended, CS should be again brought high and the DO bit
polled. If D0 is low this indicates that the internal
write-cycle is still in progress, however the D0 bit will
change to a high value when the internal write-cycle has
Rev. 1.40
22
July 28, 2009
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
