HT46R63/HT46C63
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:
S
Y
S
S
Y
S
S
Y
S
A/D Conversion Timing
PWM
and the output function of PDi is enabled, writing ²1² to
PDi data register will enable the PWMi output function.
Otherwise the PDi will stay at ²0². The PWM modulation
frequency, PWM cycle frequency and PWM cycle duty
are summarized in the following table.
The micro-controller provides 4 channels (6+2) bits
PWM outputs shared with PD0~PD3. The PWM chan-
nels has their data register. The PWMs uses a PWM
counter whose stages are 8 (stage 1~stage 8: fSYS/21 ~
f
SYS/28). The frequency source of the PWM counter co-
PWMi Modulation PWMi Cycle
PWMi Cycle
Duty
mes from fSYS. The PWM register is an eight bits regis-
ter. The waveforms of PWM outputs are as shown.
Once the PDi (i=0~3) is selected as the PWMi output
Frequency
Frequency
fSYS/64
fSYS/256
[PWM]/256
S
Y
S
[
[
[
[
P
P
P
P
W
W
W
W
M
M
M
M
]
]
]
]
=
=
=
=
1
1
1
1
0
0
0
0
0
1
2
3
P
P
P
P
W
W
W
W
M
M
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2
5
/
6
4
2
2
2
2
5
5
6
6
/
/
/
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6
6
6
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4
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6
6
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6
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P
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:
6
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0
P
W
M
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:
2
5
6
/
f
PWM Mode
Rev. 1.90
24
May 17, 2004
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
