HT45R38
The following diagram illustrates the waveforms associated with the 7+1 mode of PWM operation. It is important to
note how the single PWM cycle is subdivided into 2 individual modulation cycles, numbered 0 and 1 and how the AC
value is related to the PWM value.
S
Y
S
[
P
W
M
]
=
1
0
0
P
W
M
5
5
5
0
1
1
/
/
/
1
1
1
2
2
2
8
8
8
5
0
/
1
2
8
5
5
5
5
0
1
1
2
/
/
/
/
1
1
1
1
2
2
2
2
8
8
8
8
[
P
W
M
]
=
1
0
1
P
W
M
5
0
/
1
2
8
[
P
W
M
]
=
1
0
2
P
W
M
5
1
/
1
2
8
[
P
W
M
]
=
1
0
3
P
W
M
5
1
/
1
2
8
5
2
/
1
2
8
P
W
M
m
o
d
u
l
a
t
i
o
n
p
e
r
i
o
d
:
1
2
8
/
f
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
0
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
1
M
o
d
u
l
a
t
i
o
n
c
y
c
l
e
0
P
W
M
c
y
c
l
e
:
2
5
6
/
f
7+1 PWM Mode
b
7
b
0
P
W
M
R
e
g
i
s
t
e
r
(
7
+
1
)
M
o
d
e
A
D
C
v
a
l
u
u
e
C
v
a
l
e
PWM Register for 7+1 Mode
·
PWM Output Control
the PWM data to appear on the pin. Writing a ²0² to
the corresponding bit in the PAoutput data register will
disable the PWM output function and force the output
low. In this way, the Port A data output register can be
used as an on/off control for the PWM function. Note
that if the configuration options have selected the
PWM function, but a ²1² has been written to its corre-
sponding bit in the PAC control register to configure
the pin as an input, then the pin can still function as a
normal input line, with pull-high resistor configuration
options.
The PWM outputs are pin-shared with the Port A I/O
pins. To operate as PWM outputs and not as I/O pins,
the correct PWM configuration options must be se-
lected. A²0² must also be written to the corresponding
bits in the I/O port control register PAC to ensure that
the required PWM output pins are setup as outputs.
After these two initial steps have been carried out, and
of course after the required PWM value has been writ-
ten into the PWM register, writing a ²1² to the corre-
sponding bit in the PA output data register will enable
clr PAC.0
clr PAC.1
; set pin PA0 as output
; set pin PA1 as output
set pa.0
; PA.0=1; enable pin ²PA0/PWM0² to be the PWM channel 0
mov a,64h
mov pwm0,a
; PWM0=100D=64H
set pa.1
; PA.1=1; enable pin ²PA1/PWM1² to be the PWM channel 1
mov a,65h
mov pwm1,a
; PWM1=101D=65H
clr pa.0
clr pa.1
; disable PWM0 output - PA.0 will remain low
; disable PWM1 output - PA.1 will remain low
Rev. 1.00
24
December 13, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
