HT45R38
Pulse Width Modulator
time constant loads will average out the pulses of the
PWM output. The difference between what is known as
the PWM cycle frequency and the PWM modulation fre-
quency should be understood. As the PWM clock is the
system clock, fSYS, and as the PWM value is 8-bits wide,
the overall PWM cycle frequency is fSYS/256. However,
when in the 7+1 mode of operation the PWM modulation
frequency will be fSYS/128, while the PWM modulation
frequency for the 6+2 mode of operation will be fSYS/64.
Each device contains a dual channel internal PWM
function. Useful for such applications such as motor
speed control, the PWM function provides outputs with
a fixed frequency but with a duty cycle that can be varied
by placing particular values into the corresponding
PWM register.
A single register, located in the Data Memory is as-
signed to each of the two PWM outputs. These registers
assume the names PWM0 and PWM1. It is here that the
8-bit value, which represents the overall duty cycle of
one modulation cycle of the output waveform, should be
placed. To increase the PWM modulation frequency,
each modulation cycle is modulated into two or four indi-
vidual modulation sub-sections, known as the 7+1
mode or 6+2 mode respectively. Each device can
choose which mode to use by selecting the appropriate
configuration option. When a mode configuration option
is chosen, it applies to both of the PWM outputs on the
device. Note that when using the PWM it is only neces-
sary to write the required value into the appropriate
PWM register and select the required mode configura-
tion option, the subdivision of the waveform into its
sub-modulation cycles is done automatically within the
microcontroller hardware.
PWM Modulation Fre- PWM Cycle PWM Cycle
Duty
quency
Frequency
fSYS/64 for (6+2) bits mode
f
SYS/256 [PWM]/256
f
SYS/128 for (7+1) bits mode
·
6+2 PWM Mode
Each full PWM cycle, as it is controlled by an 8-bit
PWM register, has 256 clock periods. However, in the
6+2 PWM Mode, each PWM cycle is subdivided into
four individual sub-cycles known as modulation cycle
0 ~ modulation cycle 3, denoted as ²i² in the table.
Each one of these four sub-cycles contains 64 clock
cycles. In this mode, a modulation frequency increase
by a factor of four is achieved. The 8-bit PWM register
value, which represents the overall duty cycle of the
PWM waveform, is divided into two groups. The first
group which consists of bit2~bit7 is denoted here as
the DC value. The second group which consists of
bit0~bit1 is known as the AC value. In the 6+2 PWM
mode, the duty cycle value of each of the four modula-
tion sub-cycles is shown in the following table.
The PWM clock source is the system clock fSYS
.
PWM Register
Name
PWM Mode
Output Pin
6+2 or 7+1
6+2 or 7+1
PA0
PA1
PWM0
PWM1
DC
Parameter
AC (0~3)
i<AC
(Duty Cycle)
DC
64
PWM Function Table
1
This method of dividing the original modulation cycle
into a further 2 or 4 sub-cycles enables the generation of
higher PWM frequencies, which allow a wider range of
applications to be served. As long as the periods of the
generated PWM pulses are less than the time constants
of the load, the PWM output will be suitable as such long
Modulation cycle i
(i=0~3)
DC
64
i³AC
6+2 Mode Modulation Cycle Values
Rev. 1.00
22
December 13, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
