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HT45R38 参数 Datasheet PDF下载

HT45R38图片预览
型号: HT45R38
PDF下载: 下载PDF文件 查看货源
内容描述: C / R键F型8位OTP MCU [C/R to F Type 8-Bit OTP MCU]
分类和应用:
文件页数/大小: 49 页 / 347 K
品牌: HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
 浏览型号HT45R38的Datasheet PDF文件第5页浏览型号HT45R38的Datasheet PDF文件第6页浏览型号HT45R38的Datasheet PDF文件第7页浏览型号HT45R38的Datasheet PDF文件第8页浏览型号HT45R38的Datasheet PDF文件第10页浏览型号HT45R38的Datasheet PDF文件第11页浏览型号HT45R38的Datasheet PDF文件第12页浏览型号HT45R38的Datasheet PDF文件第13页  
HT45R38  
therefore occur. In other words, using the table read  
instruction in the main routine and also in the ISR  
should be avoided. However, if the table read instruc-  
tion has to be used in both the main routine and in the  
ISR, the interrupt should be disabled prior to the table  
read instruction execution. The interrupt should not be  
re-enabled until the TBLH has been backed up. All ta-  
ble related instructions require two cycles to complete  
the operation. These areas may function as normal  
program memory depending upon the requirements.  
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Stack Register - STACK  
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This is a special part of the memory which is used to save  
the contents of the program counter only. The stack is  
organised into 6-levels and is neither part of the data nor  
part of the program space, and is neither readable nor  
writable. The activated level is indexed by the stack  
pointer (SP) and is neither readable nor writeable. At a  
subroutine call or interrupt acknowledgment, the con-  
tents of the program counter are pushed onto the stack.  
At the end of a subroutine or an interrupt routine, signaled  
by a return instruction, RET or RETI, the program counter  
is restored to its previous value from the stack. After a de-  
vice reset, the SP will point to the top of the stack.  
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If the stack is full and a non-masked interrupt takes  
place, the interrupt request flag will be recorded but the  
acknowledgment will be inhibited. When the stack  
pointer is decremented, by RET or RETI, the interrupt  
will be serviced. This feature prevents stack overflow al-  
lowing the programmer to use the structure more easily.  
In a similar case, if the stack is full and a ²CALL² is sub-  
sequently executed, stack overflow occurs and the first  
entry will be lost as only the most recent 6 return ad-  
dresses are stored.  
1
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Data Memory - RAM  
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The data memory has a capacity of 230´8 bits. The data  
memory is divided into two functional groups: special  
function registers and general purpose data memory  
(192´8). Most are read/write, but some are read only.  
2
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The special function registers include the Indirect ad-  
dressing registers (00H, 02H), Timer/Event Counter 0  
(TMR;0DH), Timer/Event Counter 0 control register  
(TMR0C;0EH), Timer/Event Counter 1 (TMR1;10H),  
Timer/Event Counter 1 control register (TMR1C;11H),  
Program counter lower-order byte register (PCL;06H),  
Memory pointer registers (MP0;01H, MP1;03H), Accu-  
mulator (ACC;05H), Table pointer (TBLP;07H), Table  
higher-order byte register (TBLH;08H), Watchdog Timer  
option setting register (WDTS;09H), Status register  
(STATUS;0AH), Interrupt control register 0 (INTC0;  
0BH), Interrupt control register 1 (INTC1;1EH), Analog  
switch control register (ASCR;1CH), PWM data register  
(PWM0;1AH, PWM1;1BH), the Timer/Event Counter A  
higher-order byte register (TMRAH;20H), the  
Timer/Event Counter A lower-order byte register  
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RAM Mapping  
(TMRAL;21H), the RC oscillation converter control reg-  
ister (RCOCCR;22H), the Timer/Event Counter B  
higher-order byte register (TMRBH;23H), the  
Timer/Event Counter B lower-order byte register  
(TMRBL;24H), and the RC oscillator control register  
(RCOCR;25H), the A/D result lower-order byte register  
(ADRL;28H), the A/D result higher-order byte register  
(ADRH;29H), the A/D control register (ADCR;2AH), the  
Rev. 1.00  
9
December 13, 2006