HT45R38
therefore occur. In other words, using the table read
instruction in the main routine and also in the ISR
should be avoided. However, if the table read instruc-
tion has to be used in both the main routine and in the
ISR, the interrupt should be disabled prior to the table
read instruction execution. The interrupt should not be
re-enabled until the TBLH has been backed up. All ta-
ble related instructions require two cycles to complete
the operation. These areas may function as normal
program memory depending upon the requirements.
0
0
0
1
H
H
I
n
d
i
r
e
c
t
A
d
d
r
e
s
s
i
n
g
R
e
g
i
s
t
e
r
0
M
P
0
0
2
H
I
n
d
i
r
e
c
t
A
d
d
r
e
s
s
i
n
g
R
e
g
i
s
t
e
r
1
0
3
H
M
P
1
0
4
H
0
5
H
A
C
C
0
6
H
P
C
L
0
7
H
T
B
L
P
0
8
H
T
B
L
H
0
9
H
W
D
T
S
0
0
A
B
H
S
T
A
T
U
S
Stack Register - STACK
H
I
N
T
C
0
0
C
H
This is a special part of the memory which is used to save
the contents of the program counter only. The stack is
organised into 6-levels and is neither part of the data nor
part of the program space, and is neither readable nor
writable. The activated level is indexed by the stack
pointer (SP) and is neither readable nor writeable. At a
subroutine call or interrupt acknowledgment, the con-
tents of the program counter are pushed onto the stack.
At the end of a subroutine or an interrupt routine, signaled
by a return instruction, RET or RETI, the program counter
is restored to its previous value from the stack. After a de-
vice reset, the SP will point to the top of the stack.
0
D
H
T
M
R
0
0
E
H
T
M
R
0
C
0
F
H
H
1
1
0
1
T
M
R
1
H
T
M
R
1
C
1
2
H
P
A
1
3
H
P
P
A
B
C
C
1
4
H
P
B
1
5
H
S
p
e
c
i
a
l
P
u
r
p
o
s
e
D
a
t
a
M
e
m
o
r
y
1
6
H
P
C
1
7
H
P
C
C
1
8
H
P
E
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented, by RET or RETI, the interrupt
will be serviced. This feature prevents stack overflow al-
lowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is sub-
sequently executed, stack overflow occurs and the first
entry will be lost as only the most recent 6 return ad-
dresses are stored.
1
9
H
P
E
C
1
1
A
B
H
H
P
P
W
W
M
M
0
1
1
C
H
H
A
S
C
R
1
D
1
E
H
I
N
T
C
1
1
F
H
2
2
0
1
H
H
T
M
R
A
H
T
M
R
A
L
2
2
H
R
C
O
C
C
R
2
3
H
T
M
R
B
H
2
4
H
Data Memory - RAM
T
M
R
B
L
2
5
H
R
C
O
C
R
The data memory has a capacity of 230´8 bits. The data
memory is divided into two functional groups: special
function registers and general purpose data memory
(192´8). Most are read/write, but some are read only.
2
6
H
O
P
A
C
2
7
H
2
8
H
A
D
R
L
2
9
H
A
A
D
D
R
C
H
R
The special function registers include the Indirect ad-
dressing registers (00H, 02H), Timer/Event Counter 0
(TMR;0DH), Timer/Event Counter 0 control register
(TMR0C;0EH), Timer/Event Counter 1 (TMR1;10H),
Timer/Event Counter 1 control register (TMR1C;11H),
Program counter lower-order byte register (PCL;06H),
Memory pointer registers (MP0;01H, MP1;03H), Accu-
mulator (ACC;05H), Table pointer (TBLP;07H), Table
higher-order byte register (TBLH;08H), Watchdog Timer
option setting register (WDTS;09H), Status register
(STATUS;0AH), Interrupt control register 0 (INTC0;
0BH), Interrupt control register 1 (INTC1;1EH), Analog
switch control register (ASCR;1CH), PWM data register
(PWM0;1AH, PWM1;1BH), the Timer/Event Counter A
higher-order byte register (TMRAH;20H), the
Timer/Event Counter A lower-order byte register
2
2
A
H
H
B
A
C
S
R
2
C
H
3
F
H
H
4
0
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:
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1
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"
0
0
"
F
F
H
RAM Mapping
(TMRAL;21H), the RC oscillation converter control reg-
ister (RCOCCR;22H), the Timer/Event Counter B
higher-order byte register (TMRBH;23H), the
Timer/Event Counter B lower-order byte register
(TMRBL;24H), and the RC oscillator control register
(RCOCR;25H), the A/D result lower-order byte register
(ADRL;28H), the A/D result higher-order byte register
(ADRH;29H), the A/D control register (ADCR;2AH), the
Rev. 1.00
9
December 13, 2006
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
