HT45F23/HT45F43
8-Bit Flash MCU with Op Amps & Comparators
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The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the SLEEP1 Mode
There is only one way for the device to enter the SLEEP1 Mode and that is to execute the ²HALT²
instruction in the application program with the IDLEN bit in SMOD register equal to ²0² and the WDT
or LVD on. When this instruction is executed under the conditions described above, the following will
occur:
·
The system clock and Time Base clock will be stopped and the application program will stop at the
²HALT² instruction, but the WDT or LVD will remain with the clock source coming from the fSUB
clock.
·
·
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and resume counting if the WDT clock source is selected to come from the
fSUB clock as the WDT is enabled.
·
·
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE0 Mode
There is only one way for the device to enter the IDLE0 Mode and that is to execute the ²HALT²
instruction in the application program with the IDLEN bit in SMOD register equal to ²1² and the
FSYSON bit in WDTC register equal to ²0². When this instruction is executed under the conditions
described above, the following will occur:
·
The system clock will be stopped and the application program will stop at the ²HALT² instruction,
but the Time Base clock and fSUB clock will be on.
·
·
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and resume counting if the WDT clock source is selected to come from the
fSUB clock and the WDT is enabled. The WDT will stop if its clock source originates from the system
clock.
·
·
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Entering the IDLE1 Mode
There is only one way for the device to enter the IDLE1 Mode and that is to execute the ²HALT²
instruction in the application program with the IDLEN bit in SMOD register equal to ²1² and the
FSYSON bit in WDTC register equal to ²1². When this instruction is executed under the with conditions
described above, the following will occur:
·
The system clock and Time Base clock and fSUB clock will be on and the application program will
stop at the ²HALT² instruction.
·
·
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and resume counting if the WDT is enabled regardless of the WDT clock
source which originates from the fSUB clock or from the system clock.
·
The I/O ports will maintain their present conditions.
Rev. 1.20
47
September 15, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
