HT45F23/HT45F43
8-Bit Flash MCU with Op Amps & Comparators
The SLOW Mode is sourced from the LXT or the LIRC oscillators and therefore requires these
oscillators to be stable before full mode switching occurs. This is monitored using the LTO bit in the
SMOD register.
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SLOW Mode to NORMAL Mode Switching
In SLOW Mode the system uses either the LXT or LIRC low speed system oscillator. To switch back
to the NORMAL Mode, where the high speed system oscillator is used, the HLCLK bit should be set
to ²1² or HLCLK bit is ²0², but CKS2~CKS0 is set to ²010², ²011², ²100², ²101², ²110² or ²111². As a
certain amount of time will be required for the high frequency clock to stabilise, the status of the HTO
bit is checked. The amount of time required for high speed system oscillator stabilization depends
upon which high speed system oscillator type is used.
Entering the SLEEP0 Mode
There is only one way for the device to enter the SLEEP0 Mode and that is to execute the ²HALT²
instruction in the application program with the IDLEN bit in SMOD register equal to ²0² and the WDT
and LVD both off. When this instruction is executed under the conditions described above, the following
will occur:
·
The system clock, WDT clock and Time Base clock will be stopped and the application program
will stop at the ²HALT² instruction.
·
·
The Data Memory contents and registers will maintain their present condition.
The WDT will be cleared and stopped no matter if the WDT clock source originates from the fSUB
clock or from the system clock.
Rev. 1.20
46
September 15, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
