HT37B90/HT37B70/HT37B50/HT37B30
System Architecture
A key factor in the high-performance features of the
Holtek range of Music Type microcontrollers is attrib-
uted to the internal system architecture. The range of
devices take advantage of the usual features found
within RISC microcontrollers providing increased speed
of operation and enhanced performance. The pipelining
scheme is implemented in such a way that instruction
fetching and instruction execution are overlapped,
hence instructions are effectively executed in one cycle,
with the exception of branch or call instructions. An 8-bit
wide ALU is used in practically all operations of the in-
struction set. It carries out arithmetic operations, logic
operations, rotation, increment, decrement, branch de-
cisions, etc. The internal data path is simplified by mov-
ing data through the Accumulator and the ALU. Certain
internal registers are implemented in the Data Memory
and can be directly or indirectly addressed. The simple
addressing methods of these registers along with addi-
tional architectural features ensure that a minimum of
external components is required to provide a functional
I/O and A/D control system with maximum reliability and
flexibility.
instruction cycle. Although the fetching and execution of
instructions takes place in consecutive instruction cy-
cles, the pipelining structure of the microcontroller en-
sures that instructions are effectively executed in one
instruction cycle. The exception to this are instructions
where the contents of the Program Counter are
changed, such as subroutine calls or jumps, in which
case the instruction will take one more instruction cycle
to execute. When the RC oscillator is used, OSC2 is
freed for use as a T1 phase clock synchronizing pin.
This T1 phase clock has a frequency of fOSC/8 with a 1:3
high/low duty cycle. For instructions involving branches,
such as jump or call instructions, two machine cycles
are required to complete instruction execution. An extra
cycle is required as the program takes one cycle to first
obtain the actual jump or call address and then another
cycle to actually execute the branch. The requirement
for this extra cycle should be taken into account by pro-
grammers in timing sensitive applications.
Program Counter
During program execution, the Program Counter is used
to keep track of the address of the next instruction to be
executed. It is automatically incremented by one each
time an instruction is executed except for instructions,
such as ²JMP² or ²CALL², that demand a jump to a
non-consecutive Program Memory address. Note that
the Program Counter width varies with the Program
Memory capacity depending upon which device is se-
lected. However, it must be noted that only the lower 8
bits, known as the Program Counter Low Register, are
directly addressable by user.
Clocking and Pipelining
The main system clock, derived from either a Crys-
tal/Resonator or RC oscillator. The oscillator frequency
divided by 2 is subdivided into four internally generated
non-overlapping clocks, T1~T4. The Program Counter
is incremented at the beginning of the T1 clock during
which time a new instruction is fetched. The remaining
T2~T4 clocks carry out the decoding and execution
functions. In this way, one T1~T4 clock cycle forms one
System Clocking and Pipelining
Instruction Fetching
Rev. 1.00
9
June 22, 2017
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
