HT36B0
A_R
ENV1
ENV0
Volume Control Bit
VL2~0, VR2~0
VL1~0, VR1~0
VL0, VR0
Control Bit Final Value
Mode
0
0
0
x
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
111b
11b
Release mode
No change mode
Attach mode
1b
No Bit
unchanged
000b
00b
VL2~0, VR2~0
VL1~0, VR1~0
VL0, VR0
0b
Envelope Type Definition
·
The PCM code definition
Stereo Serial Data Format
The HT36B0 can only solve the voice format of the
signed 8-bit raw PCM. And the MCU will take the voice
code 80H as the end code.
The audio output data is in serial mode with 16 bit digi-
tal signal and LSB first output. There is a high sam-
pling rate of 50kHz when the system clock is 12.8MHz
and with two channel outputs for Right/Left channel.
HT36A0 provides only one serial data format as IIS
mode. The user could directly connect a D/Aconverter
which can accept the IIS serial data format, like
HT82V731.
So each PCM code section must be ended with the end
code 80H.
D/A Converter Interface
HT36B0 provides the IIS serial data format to support the
multiple D/A converters, one bit clock output and a word
clock signal for left/right stereo serial data transmission.
Digital to Analog Converter (DAC)
The HT36B0 provides two 16-bit current type DAC de-
vice controlled by MCU or Wavetable Synthesizer for
driving external speaker through an external NPN
transistor. It is in fact an optional object used for
Wavetable Synthesizer DAC or general DAC, which is
determine by Mask Option and the DAC control regis-
ter. If general DAC is chosen for application, then the
Wavetable Synthsizer is disabled since the DAC is
taken up and controlled by the MCU. If general DAC is
selected, the programmer must write the voice data to
the registers DAL and DAH to get the corresponding
analog data.
Clock Signal
The bit clock output signals DCK are used to synchronize
the IIS serial data.
The word clock signal LOAD divides the serial data into
left channel and right channel data for two-way audio out-
put.
·
LOAD
The word clock signal LOAD is used for IIS serial data.
The stereo serial data consists of 16-channel sound
generator.
·
·
DOUT
On IIS format, a ²H² state on LOAD is used for the right
channel, and a ²L² state is used for the left channel.
DCK
DCK bit clock is the clock source for the signal.
D
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D/A Converter Timing
Rev. 1.10
20
July 3, 2008
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
