32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Table 2. HT32F125x Pin Descriptions
Pins
Description
AF1
IO
Pin
Name
Type
Level
48
LQFP
Default function
(AF0)
(Note1)
AF2
AF3
(Note2)
VSSA_2
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
1
2
3
4
5
6
7
P
Ground reference for ADC and OPA/Comparator
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GPIO PA0
ADC_IN0
ADC_IN1
ADC_IN2
ADC_IN3
ADC_IN4
ADC_IN5
ADC_IN6
ADC_IN7
GT1_ETI
GT0_CH3
GT0_CH2
GT0_CH1
GT0_CH0
SPI_MOSI
SPI_MISO
GPIO PA1
GPIO PA2
UR_DCD
UR_DSR
UR_DTR
UR_RI
GPIO PA3
GPIO PA4
GPIO PA5
8
GPIO PA6
UR_RTS/TXE SPI_SCK
UR_CTS/SCK SPI_SEL
UR_RX
9
GPIO PA7
10
11
12
5V-T
GPIO PA8
5V-T
5V-T
GPIO PA9-BOOT0
GPIO PA10-BOOT1
UR_TX
LDO 1.8 V output. Please put a 10μF capacitor to GND in those pins
as close as possible.
VLDOOUT 13
P
N.C
14
15
16
LDO 3.3 V power source, also connected to the power switch of the
backup domain.
VLDOIN
VSSLDO
P
P
I
LDO ground reference
nRST
17
18
(Backup 5V-T
domain)
External reset pin and external wakeup pin in Power-Down mode
VDD 3.3 V for backup domain
(note3)
VBAT
P
I/O
(Backup
domain)
PB8(note3) 19
PB9(note3) 20
XTAL32KIN
XTAL32KOUT
RTCOUT
PB8
PB9
I/O
(Backup
domain)
I/O
PB10-
WAKEUP
PB10
21
(Backup 5V-T
domain)
GT0_ETI
PB11
PA11
PA12
PA13
PA14
PA15
VDD33_2
VSS33_2
VSS33_3
PB12
22
23
24
25
26
27
28
29
30
31
I/O
I/O
I/O
I/O
I/O
I/O
P
5V-T
5V-T
5V-T
5V-T
5V-T
5V-T
GPIO PB11
GPIO PA11
GPIO PA12
SWDIO
CKOUT
I2C_SCL
I2C_SDA
PA13
GT0_CH3
GT0_CH2
GT0_CH1
GT0_CH0
SWCLK
PA14
TRACESWO
PA15
3.3 V voltage for digital I/O
P
Ground reference for digital I/O
Ground reference for digital core
P
I/O
5V-T
GPIO PB12
SPI_SEL
UR_DCD
GT1_CH3
Rev. 1.00
20 of 35
May 27, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
