32-bit ARM Cortex™-M3 MCU
HT32F1251/51B/52/53
Clock Structure
Prescaler
÷1, 2
CK_USART
8 MHz
PLLSRC
PLLEN
PLL
HSI RC
UREN
f CK_PLL,max = 144MHz
1
0
CK_PLL
HSIEN
STCLK
(to SysTick)
÷8
SW[1:0]
4-16 MHz
HSE XTAL
fCK_SYS,max = 144MHz
fCK_AHB,max = 72MHz
0x
11
10
AHB
CK_SYS
CK_AHB
CK_HSI
CK_HSE
FCLK
( free running clock)
Prescaler
÷ 1,2,4,8
HSEEN
HCLKC
Clock
( to Cortex-M3)
Monitor
CM3EN
(control by HW)
CK_LSE
32.768 kHz
LSE OSC
WDTSRC
HCLKF
( to Flash)
LSEEN
1
0
CK_WDT
CM3EN
FMCEN
32 kHz
LSI RC
CK_LSI
WDTEN
HCLKS
RTCSRC
( to SRAM)
CM3EN
LSIEN
PCLK
SRAMEN
( to OPA,
AFIO
1
0
CK_RTC
GPIO Port,
ADC,
SPI,
USART,
I2C,
GPTIM,
EXTI,
14
CKOUTSRC[2:0]
OPA0EN
14
WDTEN
(APB peripherals clock gating)
RTCEN
000
001
010
CK_PLL/16
CK_AHB/16
CK_SYS/16
RTC,
WDT)
CKOUT
011
100
101
110
CK_HSE/16
CK_HSI/16
CK_LSE
ADC
Prescaler
÷ 1,2,4,6,8...
CK_ADC
CK_LSI
ADCEN
Legend: HSE = High Speed External clock
HSI = High Speed Internal clock
LSE = Low Speed External clock
LSI = Low Speed Internal clock
NOTE: 1. Control bits LSIEN & LSEEN are located at RTC Control Register (RTCCR).
2. HT32F1251B does not include the VBAT, XTAL32KIN and XTAL32KOUT pins.
Figure 3. HT32F125x Clock Structure Diagram
Rev. 1.00
17 of 35
May 27, 2011
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
