HT1380A/HT1381A
R/W Signal
AM-PM Mode
TheꢀLSBꢀofꢀtheꢀCommandꢀByteꢀdeterminesꢀwhetherꢀ
theꢀdataꢀinꢀtheꢀregisterꢀbeꢀreadꢀorꢀbeꢀwrittenꢀto.
TheseꢀareꢀtwoꢀfunctionsꢀforꢀtheꢀD5ꢀofꢀtheꢀhourꢀregisterꢀ
determinedꢀbyꢀtheꢀvalueꢀD7ꢀofꢀtheꢀsameꢀregister.ꢀ
OneꢀisꢀusedꢀinꢀAM/PMꢀselectionꢀonꢀtheꢀ12-hourꢀ
mode.ꢀWhenꢀD5ꢀisꢀlogicꢀ1,ꢀꢀitꢀisꢀPM,ꢀotherwiseꢀit′sꢀ
AM.ꢀTheꢀotherꢀisꢀusedꢀtoꢀsetꢀtheꢀsecondꢀ10-hourꢀbitꢀ
(20~23ꢀhours)ꢀonꢀtheꢀ24-hourꢀmode.
Whenꢀitꢀisꢀsetꢀasꢀ″0″ꢀmeansꢀthatꢀaꢀwriteꢀcycleꢀisꢀtoꢀtakeꢀ
placeꢀotherwiseꢀthisꢀchipꢀwillꢀbeꢀsetꢀintoꢀtheꢀreadꢀmode.
A0~A2
A0ꢀtoꢀA2ꢀofꢀtheꢀCommandꢀByteꢀisꢀusedꢀtoꢀspecifyꢀ
whichꢀregistersꢀareꢀtoꢀbeꢀaccessed.ꢀThereꢀareꢀeightꢀ
registersꢀusedꢀtoꢀcontrolꢀtheꢀmonthꢀdata,ꢀetc.,ꢀandꢀeachꢀ
ofꢀtheseꢀregistersꢀhaveꢀtoꢀbeꢀsetꢀasꢀaꢀwriteꢀcycleꢀinꢀtheꢀ
initialꢀtime.
Reset and Serial Clock Control
TheꢀRESTꢀpinꢀisꢀusedꢀtoꢀallowꢀaccessꢀdataꢀtoꢀtheꢀshiftꢀ
registerꢀlikeꢀaꢀtoggleꢀswitch.ꢀWhenꢀtheꢀRESTꢀpinꢀ
isꢀtakenꢀhigh,ꢀtheꢀbuilt-inꢀcontrolꢀlogicꢀisꢀturnedꢀonꢀ
andꢀtheꢀaddress/commandꢀsequenceꢀcanꢀaccessꢀtheꢀ
correspondingꢀshiftꢀregister.ꢀTheꢀRESTꢀpinꢀisꢀalsoꢀ
usedꢀtoꢀterminateꢀeitherꢀsingle-byteꢀorꢀburstꢀmodeꢀ
dataꢀformat.
Burst Mode
WhenꢀtheꢀCommandꢀByteꢀisꢀ10111110ꢀ(orꢀ10111111),ꢀ
theꢀHT1380A/HT1381Aꢀisꢀconfiguredꢀinꢀburstꢀmode.ꢀ
Inꢀthisꢀmodeꢀtheꢀeightꢀclock/calendarꢀregistersꢀcanꢀ
beꢀwrittenꢀ(orꢀread)ꢀinꢀseries,ꢀstartingꢀwithꢀbitꢀ0ꢀofꢀ
registerꢀaddressꢀ0ꢀ(seeꢀtheꢀtimingꢀonꢀtheꢀnextꢀpage).
TheꢀinputꢀsignalꢀofꢀSCLKꢀisꢀaꢀsequenceꢀofꢀaꢀfallingꢀ
edgeꢀfollowedꢀbyꢀaꢀrisingꢀedgeꢀandꢀitꢀisꢀusedꢀtoꢀ
synchronizeꢀtheꢀregisterꢀdataꢀwhetherꢀreadꢀorꢀwrite.ꢀ
Forꢀdataꢀinput,ꢀtheꢀdataꢀmustꢀbeꢀreadꢀafterꢀtheꢀrisingꢀ
edgeꢀofꢀSCLK.ꢀTheꢀdataꢀonꢀtheꢀI/Oꢀpinꢀbecomesꢀ
outputꢀmodeꢀafterꢀtheꢀfallingꢀedgeꢀofꢀtheꢀSCLK.ꢀAllꢀ
dataꢀtransferꢀterminatesꢀifꢀtheꢀRESTꢀpinꢀisꢀlowꢀandꢀ
theꢀI/Oꢀpinꢀgoesꢀtoꢀaꢀhighꢀimpedanceꢀstate.ꢀTheꢀdataꢀ
transferꢀisꢀillustratedꢀonꢀtheꢀnextꢀpage.
Test Mode
Whenꢀ theꢀ Commandꢀ Byteꢀ isꢀ setꢀ asꢀ 1001xxx1,ꢀ
HT1380A/HT1381Aꢀisꢀconfiguredꢀinꢀtestꢀmode.ꢀTheꢀ
testꢀmodeꢀisꢀusedꢀbyꢀHoltekꢀonlyꢀforꢀtestingꢀpurposes.ꢀ
Ifꢀusedꢀgenerally,ꢀunpredictableꢀconditionsꢀmayꢀoccur.
Data Input and Data Out
Write Protect Register
InꢀwritingꢀaꢀdataꢀbyteꢀwithꢀHT1380A/HT1381A,ꢀtheꢀ
read/writeꢀshouldꢀfirstꢀsetꢀasꢀR/W=0ꢀinꢀtheꢀCommandꢀ
Byteꢀandꢀfollowꢀwithꢀtheꢀcorrespondingꢀdataꢀregisterꢀ
onꢀtheꢀrisingꢀedgeꢀofꢀtheꢀnextꢀeightꢀSCLKꢀcycles.ꢀ
AdditionalꢀSCLKꢀcyclesꢀareꢀignored.ꢀDataꢀinputsꢀareꢀ
enteredꢀstartingꢀwithꢀbitꢀ0.
Thisꢀregisterꢀisꢀusedꢀtoꢀpreventꢀaꢀwriteꢀoperationꢀ
toꢀanyꢀotherꢀregister.ꢀDataꢀcanꢀbeꢀwrittenꢀintoꢀtheꢀ
designatedꢀregisterꢀonlyꢀifꢀtheꢀWriteꢀProtectꢀsignalꢀ
(WP)ꢀisꢀsetꢀtoꢀlogicꢀ0.ꢀTheꢀWriteꢀProtectꢀRegisterꢀ
shouldꢀbeꢀsetꢀfirstꢀbeforeꢀrestartingꢀtheꢀsystemꢀorꢀ
beforeꢀwritingꢀtheꢀnewꢀdataꢀtoꢀtheꢀsystem,ꢀandꢀitꢀ
shouldꢀsetꢀasꢀlogicꢀ1ꢀinꢀtheꢀreadꢀcycle.ꢀTheꢀWriteꢀ
Protectꢀbitꢀcannotꢀbeꢀwrittenꢀtoꢀinꢀtheꢀburstꢀmode.
InꢀreadingꢀaꢀdataꢀonꢀtheꢀregisterꢀofꢀHT1380A/
HT1381A,ꢀR/W=1ꢀshouldꢀfirstꢀbeꢀenteredꢀasꢀinput.ꢀ
Theꢀdataꢀbitꢀoutputsꢀonꢀtheꢀfallingꢀedgeꢀofꢀtheꢀnextꢀ
eightꢀSCLKꢀcycles.ꢀNoteꢀthatꢀtheꢀfirstꢀdataꢀbitꢀtoꢀbeꢀ
transmittedꢀonꢀtheꢀfirstꢀfallingꢀedgeꢀafterꢀtheꢀlastꢀbitꢀofꢀ
theꢀreadꢀcommandꢀbyteꢀisꢀwritten.ꢀAdditionalꢀSCLKꢀ
cyclesꢀre-transmitsꢀtheꢀdataꢀbytesꢀasꢀlongꢀasꢀRESTꢀ
remainsꢀatꢀhighꢀlevel.ꢀDataꢀꢀoutputsꢀareꢀreadꢀstartingꢀ
withꢀbitꢀ0.
Clock HALT Bit
D7ꢀofꢀtheꢀSecondsꢀRegisterꢀisꢀdefinedꢀasꢀtheꢀClockꢀ
HaltꢀFlagꢀ(CH).
Whenꢀthisꢀbitꢀisꢀsetꢀtoꢀlogicꢀ1,ꢀtheꢀclockꢀoscillatorꢀisꢀ
stoppedꢀandꢀtheꢀchipꢀgoesꢀintoꢀaꢀlow-powerꢀstandbyꢀ
mode.ꢀWhenꢀthisꢀbitꢀisꢀwrittenꢀtoꢀlogicꢀ0,ꢀtheꢀclockꢀ
willꢀstart.
Crystal Selection
Aꢀ32768Hzꢀcrystalꢀcanꢀbeꢀdirectlyꢀconnectedꢀtoꢀtheꢀ
HT1380A/HT1381Aꢀonꢀpinsꢀ2ꢀandꢀ3ꢀwhichꢀareꢀtheꢀ
crystalꢀX1ꢀandꢀX2ꢀpins.ꢀInꢀorderꢀtoꢀensureꢀthatꢀtheꢀ
desiredꢀfrequencyꢀisꢀachieved,ꢀitꢀisꢀrecommendedꢀ
toꢀuseꢀaꢀcrystalꢀwithꢀaꢀcapacitanceꢀofꢀ9.0pF.ꢀItꢀisꢀ
notꢀrecommendedꢀthatꢀadditionalꢀloadꢀcapacitorsꢀ
areꢀconnectedꢀtoꢀtheꢀX1ꢀandꢀX2ꢀpins.ꢀReferꢀtoꢀtheꢀ
followingꢀpageꢀforꢀtheꢀcrystalꢀspecifications.
12-hour/24-hour Mode
TheꢀD7ꢀofꢀtheꢀhourꢀregisterꢀisꢀdefinedꢀasꢀtheꢀ12-hourꢀ
orꢀ24-hourꢀmodeꢀselectꢀbit.
Whenꢀthisꢀbitꢀisꢀinꢀhighꢀlevel,ꢀtheꢀ12-hourꢀmodeꢀisꢀ
selectedꢀotherwiseꢀit′sꢀtheꢀ24-hourꢀmode.
3
2
7
H
6
z
8
X
1
X
2
Rev. 1.00
6
June 15, 2012
HOLTEK [ HOLTEK SEMICONDUCTOR INC ]
