HMC1190LP6GE
v01.1112
BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER
w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz
Table 23. Reg 17h Modes Register Register Default 1A8 h
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
Master enable for the entire VCO Subsystem
1 - Enable
0 - Disable
[0]
R/W
VCO SubSys Master Enable
1
1
Chip Enable is also required.
1: Internal VCO Enable
0: Internal VCO Disable
[1]
[2]
R/W
R/W
VCO Enable
1
1
1
0
External VCO Buffer to output stage enable. Only used when locking
an external VCO.
External VCO Buffer Enable
[3]
[4]
[5]
[6]
[7]
R/W
R/W
R/W
R/W
R/W
PLL Buffer Enable
LO Output Buffer Enable
LO2 Output Buffer Enable
External Input Enable
Pre Lock Mute Enable
1
1
1
1
1
1
0
1
0
1
PLL Buffer Enable. Used when using an internal VCO.
Enables LO (LO_P & LO_N pins) output buffer.
Enables the second (LO2_N & LO2_P pins) output buffer
Enables External VCO input
Mute both output buffers until the PLL is locked
Enables Single-Ended output mode for LO output
1- Single-ended mode, LO_N pin is enabled, and LO_P pin is
disabled
0- Differential mode, both LO_N and LO_P pins enabled
Please note that single-ended output is only available on LO_N pin.
LO Output Single-Ended
Enable
[8]
[9]
R/W
R/W
1
1
1
0
Enables Single-Ended output mode for LO2 output
1- Single-ended mode, LO2_N pin is enabled, and LO2_P pin is
disabled
0- Differential mode, both LO2_N and LO2_P pins enabled
Please note that single-ended output is only available on LO2_N pin.
LO2 Output Single-Ended
Enable
[10]
[11]
R/W
R/W
Reserved
1
1
0
0
Reserved
Connects CP to CP1 or CP2 output.
0: CP1
Charge Pump Output Select
1: CP2
Table 24. Reg 18h Bias Register Register Default 54C1 h
BIT
[18:0]
[19]
TYPE
R/W
R/W
R/W
NAME
W
19
1
DEFLT
DESCRIPTION
Reserved
54C1h
Reserved
External Input buffer BIAS bit0
External Input buffer BIAS bit1
0
0
External Input buffer BIAS bit0
External Input buffer BIAS bit1
[20]
1
Table 25. Reg 19h Cals Register Register Default 19 h
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
[23:0]
R/W
Reserved
24
19h
Table 26. Reg 1Ah Seed Register Register Default B29DOB h
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
Used to program output phase relative to the reference signal.
Phase = 2π(Reg 20h/224). To exactly program output phase
operation in Exact Frequency Mode is required. When not using
Exact Frequency Mode Reg 20h sets the start phase of output
signal. If Reg 06h[8] = 1, Reg 20h sets the start phase of the signal
after every frequency change.
[23:0]
R/W
Delta Sigma Modulator Seed
24
B29D0Bh
For price, delivery and to place orders: Hittite Microwave Corporation, 2 Elizabeth Drive, Chelmsford, MA 01824
Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
32
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