HMC1190LP6GE
v01.1112
BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER
w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz
Table 13. Reg 0Bh PD/CP Register Default 78061 h
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
[3:0]
R/W
Reserved
4
1
Reserved
Inverts the PD polarity (program to 0)
0- Use with a positive tuning slope VCO and Passive Loop Filter
(default)
[4]
R/W
PD Phase Select
1
0
1- Use with a Negative Slope VCO or with an inverting Active Loop
Filter with a Positive Slope VCO
[5]
[6]
R/W
R/W
R/W
PD Up Output Enable
PD Down Output Enable
Reserved
1
1
2
1
1
0
Enables the PD UP output, see also Reg 0Bh Reg 7h[9]
Enables the PD DN output, see alsoReg 0Bh Reg 7h [10]
Reserved, .
[8:7]
Forces CP UP output on if CP is not forced down - Use for Test
only
[9]
[10]
[11]
R/W
R/W
R/W
Force CP UP
Force CP DN
1
1
0
0
0
Forces CP DN output on if CP is not forced up - Use for Test only
Force CP MId Rail - Use for Test only (if Force CP UP or Force CP
DN are enabled they have precedence)
Force CP MId Rail
1
12
[23:12]
R/W
Reserved
78h
Reserved.
Table 14. Reg 0Ch Exact Frequency Register
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
Comparison Frequency divided by the correction rate. Must be an
integer. Frequencies at exactly the correction rate will have zero
frequency error (Exact Frequency Mode). Only works in modulator
Mode B (3rd order modulator type (Reg 06h[3:2] = 2h)). Reg 0Ch
must be 0 if using other DSM types ie. if Reg 06h[3:2] ≠ 2h.
0: Disabled
[23:0]
R/W
Number of Channels per Fpd
24
0
1: Invalid
≥ 2 valid
max: 224-1 = FFFFFFh = 16,777,215d
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28
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