HMC1190LP6GE
v01.1112
BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER
w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz
Table 15. Reg 0Fh GPO Register
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
Select signal to be output to SDO pin when enabled
DEFAULT LOCK DETECT
0: Data from Reg0F[5]
1: Lock Detect Output
2. Lock Detect Trigger
3: Lock Detect Window Output
4: Ring Osc Test
5. Pullup Hard from CSP
6. PullDN hard from CSP
7. Reserved
8: Reference Buffer Output
9: Ref Divider Output
10: VCO divider Output
11. Modulator Clock from VCO divider
12. Auxiliary Clock
[4:0]
R/W
GPO
5
1
13. Aux SPI Clock
14. Aux SPI Enable
15. Aux SPI Data Out
16. PD DN
17. PD UP
18. SD3 Clock Delay
19. SD3 Core Clock
20. AutoStrobe Integer Write
21. Autostrobe Frac Write
22. Autostrobe Aux SPI
23. SPI Latch Enable
24. VCO Divider Sync Reset
25. Seed Load Strobe
26.-29 Not Used
30. SPI Output Buffer En
31. Soft RSTB
[5]
[6]
R/W
R/W
GPO Test Data
1
1
0
0
1 - GPO Test Data when GPO_Select = 0
1- Outputs GPO data only
0- Automuxes between SDO and GPO data
Prevent Automux SDO
Only for HMC SPI mode
[7]
R/W
R/W
LDO Driver Always On
Reserved
1
1
0
0
1- LD_SDO Pin driver always on
0- LD_SDO Pin driver only on during SPI read cycle
[9:8]
Reserved
Table 16. Reg 10h Tuning Register (Read Only)
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
VCO sub-band selection.
0- maximum frequency
[7:0]
R
VCO Tune Curve
8
80h
‘1111 1111’b- minimum frequency
Indicates if the VCO tuning is in process
[8]
R
VCO Tuning Busy
1
0
1- Busy
0- Not Busy
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Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
29
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