HMC1190LP6GE
v01.1112
BROADBAND HIGH IP3 DUAL CHANNEL DOWNCONVERTER
w/ Fractional-N PLL & VCO, 0.7 - 3.5 GHz
REGISTER MAP
Table 1. Reg 00h ID Register (Read Only) DEFAULT C7701A h
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
[23:0]
RO
Chip ID
24
C7701A
Chip ID Number
Table 2. Reg 00h Read Address Register (Write Only)
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
(WRITE ONLY) Specifies the address to be read in the next read
cycle.
[4:0]
WO
Read Address
5
-
[5]
WO
WO
Soft Reset
1
-
-
(WRITE ONLY) Soft Reset - (set to 0 during operation)
Not defined, set to 0h.
[23:6]
Not Defined
18
Table 3. Reg 01h Chip Enable Register DEFAULT 3h
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
1 = Chip enable via CHIP_EN pin, Reg 01h[0]=1 and CHIP_EN pin
low places the PLL in Power Down Mode
0 = Chip enable via SPI - Reg 01h[0] = 0, CHIP_EN pin ignored
(see Power Down Mode description for more details)
[0]
R/W
Chip Enable Pin Select
1
1
Controls Chip Enable (Power Down) if Reg 01h[0] =0
Reg 01h[0]=0 and Reg 01h[1]=1 - chip is enabled, CHIP_EN pin
don’t care
Reg 01h[0]=0 and Reg 01h[1]=0 - chip disabled, CHIP_EN pin don’t
care
[1]
R/W
SPI Chip Enable
1
1
(see Power Down Mode description for more information)
1: keeps internal bias generators on, ignores chip enable control
0: bias generators controlled automatically via chip enable control
[2]
[3]
[4]
R/W
R/W
R/W
Keep Bias On
Keep PFD Pn
Keep CP On
1
1
1
0
0
0
1: keeps PFD circuit on, ignores chip enable control
0: PFD circuit controlled by chip enable control
1: keeps Charge Pump on, ignores chip enable control
0: Charge Pump automatically controlled by chip enable control
1: keeps reference buffer block on, ignores Chip enable control
0: reference buffer block automatically controlled by chip enable
control
[5]
[6]
R/W
R/W
Keep Reference Buffer ON
Keep VCO on
1
1
0
0
1: keeps VCO divider buffer on, ignores chip enable control
0: VCO divider buffer automatically controlled via chip enable
control
1: keeps GPO output Driver ON, ignores Chip enable control
0: GPO output driver automatically controlled by chip enable control
[7]
R/W
R/W
Keep GPO Driver ON
reserved
1
0
0
[9:8]
2
reserved
Table 4. Reg 02h Reference Divider Register DEFAULT 1h
BIT
TYPE
NAME
W
DEFLT
DESCRIPTION
Reference Divider ’R’ Value (EQ 8)
[13:0]
R/W
R Divider Setting
14
1
min: 1d
max: 16383d
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Phone: 978-250-3343 Fax: 978-250-3373 Order On-line at www.hittite.com
Application Support: Phone: 978-250-3343 or apps@hittite.com
23
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