4.3.2Interrupt-Related
Registers
The interrupt-related registers are the system control register (SYSCR), IRQ sense control register
(ISCR), IRQ enable register (IER), and keyboard matrix interrupt mask registers (KMIMR and
KMIMRA).
Table 4.3 Registers Read by Interrupt Controller
Name
Abbreviation
SYSCR
ISCR
Read/Write
R/W
Address
H'FFC4
H'FFC6
H'FFC7
H'FFF1
H'FFF3
System control register
IRQ sense control register
IRQ enable register
R/W
IER
R/W
Keyboard matrix interrupt mask register
Keyboard matrix interrupt mask register A
KMIMR
KMIMRA
R/W
R/W
System Control Register (SYSCR)
Bit
7
SSBY
0
6
STS2
0
5
STS1
0
4
3
2
NMIEG
0
1
0
STS0
0
XRST
HIE
0
RAME
1
Initial value
Read/Write
1
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
The valid edge on the NMI line is controlled by bit 2 (NMIEG) in the system control register.
Bit 2—NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the
falling or rising edge of the NMI input signal.
Bit 2: NMIEG
Description
0
1
An interrupt is generated on the falling edge of NMI.
An interrupt is generated on the rising edge of NMI.
(Initial state)
See section 3.2, System Control Register, for information on the other SYSCR bits.
IRQ Sense Control Register (ISCR)
Bit
7
6
5
4
3
2
1
0
IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
Initial value
Read/Write
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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HITACHI [ HITACHI SEMICONDUCTOR ]
