4.3.3
External Interrupts
The nine external interrupts are NMI and IRQ0 to IRQ7. NMI, IRQ0, IRQ1, IRQ2, and IRQ6 can be
used to recover from software standby mode.
NMI: A nonmaskable interrupt is generated on the rising or falling edge of the NMI input signal
regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is selected by the
NMIEG bit in the system control register. The NMI vector number is 3. In the NMI hardware
exception-handling sequence the I bit in the CCR is set to 1.
IRQ0 to IRQ7: These interrupt signals are level-sensed or sensed on the falling edge of the input,
as selected by ISCR bits IRQ0SC to IRQ7SC. These interrupts can be masked collectively by the I
bit in the CCR, and can be enabled and disabled individually by setting and clearing bits IRQ0E to
IRQ7E in the IRQ enable register.
The IRQ6 input signal can be logically ORed internally with the key sense input signals. When
KEYIN0 to KEYIN15 pins (P60 to P67 and PA0 to PA7) are used for key sense input, the
corresponding KMIMR bits should be cleared to 0 to enable the corresponding key sense input
interrupts. KMIMR bits corresponding to unused key sense inputs should be set to 1 to disable the
interrupts. All 16 key sense interrupts are combined into a single IRQ6 interrupt.
When one of these interrupts is accepted, the I bit is set to 1. IRQ0 to IRQ7 have interrupt vector
numbers 4 to 11. They are prioritized in order from IRQ7 (low) to IRQ0 (high). For details, see
table 4.2.
Interrupts IRQ0 to IRQ7 do not depend on whether pins IRQ0 to IRQ7 are input or output pins.
When using external interrupts IRQ0 to IRQ7, clear the corresponding DDR bits to 0 to set these
pins to the input state, and do not use these pins as input or output pins for the timers, serial
communication interface, I2C bus interface, host interface, or A/D converter.
4.3.4
Internal Interrupts
Twenty-six internal interrupts can be requested by the on-chip supporting modules. Each interrupt
source has its own vector number, so the interrupt-handling routine does not have to determine
which interrupt has occurred. All internal interrupts are masked when the I bit in the CCR is set to
1. When one of these interrupts is accepted, the I bit is set to 1 to mask further interrupts (except
NMI). The vector numbers are 12 to 37. For the priority order, see table 4.2.
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