Bits 7 to 0—IRQ7 to IRQ0 Sense Control (IRQ7SC to IRQ0SC): These bits determine whether
IRQ7 to IRQ0 are level-sensed or sensed on the falling edge.
Bits 7 to 0:
IRQ7SC to IRQ0SC
Description
0
1
An interrupt is generated when IRQ7 to IRQ0 inputs are low. (Initial state)
An interrupt is generated by the falling edge of the IRQ7 to IRQ0 inputs.
IRQ Enable Register (IER)
Bit
7
IRQ7E
0
6
IRQ6E
0
5
IRQ5E
0
4
IRQ4E
0
3
IRQ3E
0
2
IRQ2E
0
1
IRQ1E
0
0
IRQ0E
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 to 0—IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits enable or disable the IRQ7 to
IRQ0 interrupts individually.
Bits 7 to 0:
IRQ7E to IRQ0E
Description
0
1
IRQ7 to IRQ0 interrupt requests are disabled.
IRQ7 to IRQ0 interrupt requests are enabled.
(Initial state)
When edge sensing is selected (by setting bits IRQ7SC to IRQ0SC to 1), it is possible for an
interrupt-handling routine to be executed even though the corresponding enable bit (IRQ7E to
IRQ0E) is cleared to 0 and the interrupt is disabled. If an interrupt is requested while the enable bit
(IRQ7E to IRQ0E) is set to 1, the request will be held pending until served. If the enable bit is
cleared to 0 while the request is still pending, the request will remain pending, although new
requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to 0, the
interrupt-handling routine can be executed even though the enable bit is now 0.
If execution of interrupt-handling routines under these conditions is not desired, it can be avoided
by using the following procedure to disable and clear interrupt requests.
1.Set the I bit to 1 in the CCR, masking interrupts. Note that the I bit is set to
when execution jumps to an interrupt vector.
2.Clear the desired bits from IRQ7E to IRQ0E to 0 to disable new interrupt request
3.Clear the corresponding IRQ7SC to IRQ0SC bits to 0, then set them to 1 again. P
interrupt requests are cleared when I = 1 in the CCR, IRQnSC = 0, and IRQnE = 0.
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HITACHI [ HITACHI SEMICONDUCTOR ]
