The following sequence is carried out when reset exception handling begins.
1.The internal state of the CPU and the registers of the on-chip supporting modules a
initialized, and the I bit in the condition code register (CCR) is set to 1.
2.The CPU loads the program counter with the first word in the vector table (stored
H'0000 and H'0001) and starts program execution.
The RES pin should be held low when power is switched off, as well as when power is switched
on.
Figure 4.1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4.2 indicates the
timing in mode 1.
Vector
fetch
Internal Instruction
processing prefetch
RES/watchdog timer
reset (internal)
ø
Internal address
bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data bus
(16 bits)
(3)
(2)
(1) Reset vector address (H'0000)
(2) Starting address of program
(3) First instruction of program
Figure 4.1 Reset Sequence (Mode 2 or 3, Program Stored in On-Chip ROM)
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HITACHI [ HITACHI SEMICONDUCTOR ]
