Pin No.
FP-100B,
TFP-100B
Type
Symbol
I/O
Name and Function
Bus control
WAIT
16
I
Wait: Requests the CPU to insert wait
states into the bus cycle when an external
address is accessed.
RD
WR
AS
22
19
18
7
O
O
O
I
Read: Goes low to indicate that the CPU is
reading an external address.
Write: Goes low to indicate that the CPU is
writing to an external address.
Address strobe: Goes low to indicate that
there is a valid address on the address bus.
Interrupt signals NMI
Nonmaskable interrupt: Highest-priority
interrupt request. The NMIEG bit in the
system control register (SYSCR) determines
whether the interrupt is recognized at the
rising or falling edge of the NMI input.
IRQ0 to
23 to 25,
97 to 99,
34, 35
I
I
Interrupt request 0 to 7: Maskable interrupt
request pins.
IRQ7
Operating mode MD1
5
6
Mode: Input pins for setting the MCU mode
operating mode according to the table
below.
control
MD0
MD1 MD0 Mode
Description
*
Mode 0 Illegal setting
0
0
0
1
Mode 1 Expanded mode
with on-chip ROM
disabled
1
0
Mode 2 Expanded mode
with on-chip ROM
enabled
1
1
Mode 3 Single-chip mode
Note: * In the H8/3437SF (S-mask model,
single-power-supply on-chip flash
memory version), the settings MD1 =
MD0 = 0 are used when boot mode is
set. For details, see section 21.3,
On-Board Programming Modes.
Do not change the mode pin settings while
the chip is operating.
13
HITACHI [ HITACHI SEMICONDUCTOR ]
