Flash
EPROM Memory
Pin No.
Expanded Modes
Single-Chip Mode
Mode 3
FP-100B,
TFP-100B Mode 1
Writer
Writer
Mode
Mode 2
HIF Disabled HIF Enabled Mode
97
P84/IRQ3/TxD1 when HIF is disabled or STAC bit is 1 in STCR; NC
IOW/IRQ3 when HIF is enabled and STAC bit is 0 in STCR
NC
NC
NC
NC
98
P85/IRQ4/RxD1 when HIF is disabled or STAC bit is 1 in STCR; NC
CS2/IRQ4 when HIF is enabled and STAC bit is 0 in STCR
99
P86/SCK1/
P86/SCK1/
P86/SCK1/
P86/SCK1/
NC
IRQ5/SCL
IRQ5/SCL
IRQ5/SCL
IRQ5/SCL
100
RESO
RESO
RESO
RESO
NC
Note: Pins marked NC should be left unconnected.
For details on writer mode, refer to 18.2, Writer Mode, 19.6, Flash Memory Writer Mode
(H8/3434F), 20.6, Flash Memory Writer Mode (H8/3437F) and 21.5, Flash Memory Writer
Mode (H8/3437SF).
In this chip, except for the S-mask model (single-power-supply specification), the same pin
is used for STBY and FVPP. When this pin is driven low, a transition is made to hardware
standby mode. This occurs not only in the normal operating modes (modes 1, 2, and 3), but
also when programming flash memory with a PROM writer. When using a PROM
programmer to program dual-power-supply flash memory, therefore, the PROM
programmer specifications should provide for this pin to be held at the VCC level except
when programming (FVPP = 12 V).
*1 Differs as in mode 3, depending on whether the host interface is enabled or disabled.
*2 XDB7 to XDB6 can only be used when the host interface is enabled.
11
HITACHI [ HITACHI SEMICONDUCTOR ]
