Bit 0—Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode,
this bit enables or disables serial clock output at the SCK pin.
This bit is ignored when the external clock is selected, or when synchronous mode is selected.
For further information on the communication format and clock source selection, see table 12.8 in
section 12.3, Operation.
Bit 0: CKE0
Description
0
The SCK pin is not used by the SCI (and is available as a general-purpose I/O
port).
(Initial value)
1
The SCK pin is used for serial clock output.
12.2.7 Serial Status Register (SSR)
Bit
7
6
RDRF
0
5
ORER
0
4
FER
0
3
PER
0
2
TEND
1
1
MPB
0
0
MPBT
0
TDRE
1
Initial value
Read/Write
R/(W)*
R/(W)* R/(W)*
R/(W)* R/(W)*
R
R
R/W
Note: * Software can write a 0 to clear the flags, but cannot write a 1 in these bits.
SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 by a reset
and in the standby modes.
Bit 7—Transmit Data Register Empty (TDRE): This bit indicates when transmit data can safely
be written in TDR.
Bit 7: TDRE
Description
0
To clear TDRE, the CPU must read TDRE after it has been set to 1, then write
a 0 in this bit.
1
This bit is set to 1 at the following times:
1. When TDR contents are transferred to TSR.
2. When the TE bit in SCR is cleared to 0.
(Initial value)
243
HITACHI [ HITACHI SEMICONDUCTOR ]
