Table 12.3 Examples of BRR Settings in Asynchronous Mode (When øP = ø)
ø (MHz)
2
2.097152
Error
(%)
Bit Rate
(bits/s)
Error
(%)
n
1
N
n
1
N
110
141 +0.03
103 +0.16
207 +0.16
103 +0.16
148 –0.04
108 +0.21
217 +0.21
108 +0.21
150
1
1
300
0
0
600
0
0
1200
2400
4800
9600
19200
31250
38400
0
51
25
12
—
—
1
+0.16
+0.16
+0.16
—
0
54
26
13
6
–0.70
+1.14
–2.48
–2.48
—
0
0
0
0
—
—
0
0
—
—
—
—
—
—
—
0
—
—
—
—
—
ø (MHz)
2.4576
Error
(%)
174 –0.26
3
3.6864
Error
4
Bit Rate
(bits/s)
Error
(%)
Error
(%)
n
1
1
0
0
0
0
0
0
0
—
0
N
n
2
1
1
0
0
0
0
0
0
0
—
N
n
2
1
1
0
0
0
0
0
0
—
0
N
(%)
n
2
N
110
52
+0.50
64
191
95
191
95
47
23
11
5
+0.70
70
+0.03
150
127
255
127
63
31
15
7
0
0
0
0
0
0
0
0
—
0
155 +0.16
77 +0.16
155 +0.16
0
0
0
0
0
0
0
0
—
0
1
207 +0.16
103 +0.16
207 +0.16
103 +0.16
300
1
600
0
1200
2400
4800
9600
19200
31250
38400
77
38
19
9
+0.16
+0.16
–2.34
–2.34
–2.34
0
0
0
51
25
12
—
3
+0.16
+0.16
+0.16
—
0
0
3
4
—
0
—
2
—
2
0
1
—
—
—
—
—
Note: If possible, the error should be within 1%.
247
HITACHI [ HITACHI SEMICONDUCTOR ]
