Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight internal
clock sources obtained by dividing the supporting-module clock (øP).
Bit 2: CKS2
Bit 1: CKS1
Bit 0: CKS0
Description
øP/2
0
0
0
1
0
1
0
1
0
1
(Initial value)
øP/8
1
0
1
øP/32
øP/128
øP/256
øP/1024
øP/2048
øP/4096
1
From the clock source frequency, the resolution, period, and frequency of the PWM output can be
calculated as follows.
Resolution = 1/clock source frequency
PWM period = resolution × 250
PWM frequency = 1/PWM period
If the øP clock frequency is 10 MHz, then the resolution, period, and frequency of the PWM output
for each clock source are as shown in table 10.3.
Table 10.3 PWM Timer Parameters for 10 MHz System Clock
Internal Clock Frequency
Resolution
PWM Period
50 µs
PWM Frequency
20 kHz
5
øP/2
200 ns
øP/88 ns
øP/32
200
µs
kH
3.2 µs
800 µs
ms
1.25 kHz
312.5
øP/12812.8 µs
øP/256
3.2
H
25.6 µs
6.4 ms
25.6 ms
ms
156.3 Hz
39.1 Hz
19.5
øP/1024
102.4 µs
øP/2048204.8 µs
øP/4096
51.2
Hz
409.6 µs
102.4 ms
9.8 Hz
216
HITACHI [ HITACHI SEMICONDUCTOR ]
