10.2.2 Duty Register (DTR)
Bit
7
6
5
4
3
2
1
0
Initial value
Read/Write
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTR is an 8-bit readable/writable register that specifies the duty cycle of the output pulse. Any
duty cycle from 0% to 100% can be output by setting the corresponding value in DTR. The
resolution is 1/250. Writing 0 (H'00) in DTR gives a 0% duty cycle. Writing 125 (H'7D) gives a
50% duty cycle. Writing 250 (H'FA) gives a 100% duty cycle.
The DTR and TCNT values are always compared. When the values match, the PWM output is
placed in the 0 state.
DTR is double-buffered. A new value written in DTR does not become valid until after the timer
count changes from H'F9 to H'00. While the OE bit is cleared to 0 in TCR, however, new values
written in DTR become valid immediately. When DTR is read, the value read is the currently valid
value.
DTR is initialized to H'FF by a reset and in the standby modes.
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HITACHI [ HITACHI SEMICONDUCTOR ]
