Bit 4—Reserved: This bit is always read as 1. It cannot be written.
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of TCOR–TCNT
compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of
compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A on
the output level.
If compare-match A and B occur simultaneously, any conflict is resolved according to the
following priority order: toggle > 1 output > 0 output.
When all four output select bits are cleared to 0 the timer output signal is disabled.
After a reset, the timer output is 0 until the first compare-match event.
Bit 3: OS3
Bit 2: OS2
Description
0
0
1
0
1
No change when compare-match B occurs. (Initial value)
Output changes to 0 when compare-match B occurs.
Output changes to 1 when compare-match B occurs.
Output inverts (toggles) when compare-match B occurs.
1
Bit 1: OS1
Bit 0: OS0
Description
0
0
1
0
1
No change when compare-match A occurs. (Initial value)
Output changes to 0 when compare-match A occurs.
Output changes to 1 when compare-match A occurs.
Output inverts (toggles) when compare-match A occurs.
1
197
HITACHI [ HITACHI SEMICONDUCTOR ]
