9.2.4
Timer Control/Status Register (TCSR)
Bit
7
6
CMFA
0
5
OVF
0
4
—
1
3
OS3
0
2
OS2
0
1
OS1
0
0
OS0
0
CMFB
0
Initial value
Read/Write
R/(W)*
R/(W)* R/(W)*
—
R/W
R/W
R/W
R/W
Note: * Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
TCSR is an 8-bit readable and partially writable register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal.
TCSR is initialized to H'10 by a reset and in the standby modes.
Bit 7—Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count
matches the time constant set in TCORB. CMFB must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 7: CMFB
Description
0
To clear CMFB, the CPU must read CMFB after it has been set to 1 then write
a 0 in this bit.
(Initial value)
1
This bit is set to 1 when TCNT = TCORB.
Bit 6—Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count
matches the time constant set in TCORA. CMFA must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 6: CMFA
Description
0
To clear CMFA, the CPU must read CMFA after it has been set to 1, then write
a 0 in this bit.
(Initial value)
1
This bit is set to 1 when TCNT = TCORA.
Bit 5—Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows
(changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 5: OVF
Description
0
To clear OVF, the CPU must read OVF after it has been set to 1, then write a 0
in this bit.
(Initial value)
1
This bit is set to 1 when TCNT changes from H'FF to H'00.
196
HITACHI [ HITACHI SEMICONDUCTOR ]
