Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and
ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for
the timer counter. Six internal clock sources, derived by prescaling the system clock, are available
for each timer channel. For internal clock sources the counter is incremented on the falling edge of
the internal clock. For an external clock source, these bits can select whether to increment the
counter on the rising or falling edge of the clock input (TMCI), or on both edges.
TCR
STCR
Bit 2: Bit 1: Bit 0:
Bit 1: Bit 0:
Channel CKS2 CKS1 CKS0
ICKS1 ICKS0 Description
0
0
0
0
1
—
—
0
No clock source (timer stopped) (Initial value)
øP/8 internal clock, counted on falling edge
øP/2 internal clock, counted on falling edge
øP/64 internal clock, counted on falling edge
øP/32 internal clock, counted on falling edge
øP/1024 internal clock, counted on falling edge
øP/256 internal clock, counted on falling edge
No clock source (timer stopped)
1
1
0
1
0
1
0
1
1
0
0
1
0
1
0
1
—
External clock source, counted on rising edge
External clock source, counted on falling edge
External clock source, counted on both rising
and falling edges
1
0
1
0
1
—
0
—
No clock source (timer stopped) (Initial value)
øP/8 internal clock, counted on falling edge
øP/2 internal clock, counted on falling edge
øP/64 internal clock, counted on falling edge
øP/128 internal clock, counted on falling edge
øP/1024 internal clock, counted on falling edge
øP/2048 internal clock, counted on falling edge
No clock source (timer stopped)
1
0
1
0
1
0
1
1
0
1
0
1
0
1
—
External clock source, counted on rising edge
External clock source, counted on falling edge
External clock source, counted on both rising
and falling edges
195
HITACHI [ HITACHI SEMICONDUCTOR ]
