9.2.3
Timer Control Register (TCR)
Bit
7
6
5
OVIE
0
4
3
2
CKS2
0
1
CKS1
0
0
CKS0
0
CMIEB CMIEA
CCLR1 CCLR0
Initial value
Read/Write
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCR is an 8-bit readable/writable register that selects the clock source and the time at which the
timer counter is cleared, and enables interrupts.
TCR is initialized to H'00 by a reset and in the standby modes.
For timing diagrams, see section 9.3, Operation.
Bit 7—Compare-match Interrupt Enable B (CMIEB): This bit selects whether to request
compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer
control/status register (TCSR) is set to 1.
Bit 7: CMIEB
Description
0
1
Compare-match interrupt request B (CMIB) is disabled.
Compare-match interrupt request B (CMIB) is enabled.
(Initial value)
Bit 6—Compare-match Interrupt Enable A (CMIEA): This bit selects whether to request
compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in TCSR is set to 1.
Bit 6: CMIEA
Description
0
1
Compare-match interrupt request A (CMIA) is disabled.
Compare-match interrupt request A (CMIA) is enabled.
(Initial value)
193
HITACHI [ HITACHI SEMICONDUCTOR ]
